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138
cores/wb/wb_arbiter/rtl/arbiter.v
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138
cores/wb/wb_arbiter/rtl/arbiter.v
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/**
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* Module: arbiter
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*
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* Description:
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* A look ahead, round-robing parameterized arbiter.
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*
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* <> request
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* each bit is controlled by an actor and each actor can 'request' ownership
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* of the shared resource by bring high its request bit.
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*
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* <> grant
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* when an actor has been given ownership of shared resource its 'grant' bit
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* is driven high
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*
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* <> select
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* binary representation of the grant signal (optional use)
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*
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* <> active
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* is brought high by the arbiter when (any) actor has been given ownership
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* of shared resource.
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*
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*
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* Created: Sat Jun 1 20:26:44 EDT 2013
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*
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* Author: Berin Martini // berin.martini@gmail.com
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*/
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`ifndef _arbiter_ `define _arbiter_
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`include "clog2.vh"
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module arbiter
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#(parameter
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NUM_PORTS = 6,
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SEL_WIDTH = ((NUM_PORTS > 1) ? `CLOG2(NUM_PORTS) : 1))
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(input wire clk,
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input wire rst,
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input wire [NUM_PORTS-1:0] request,
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output reg [NUM_PORTS-1:0] grant,
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output reg [SEL_WIDTH-1:0] select,
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output reg active
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);
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/**
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* Local parameters
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*/
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localparam WRAP_LENGTH = 2*NUM_PORTS;
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// Find First 1 - Start from MSB and count downwards, returns 0 when no
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// bit set
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function [SEL_WIDTH-1:0] ff1 (
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input [NUM_PORTS-1:0] in
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);
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reg set;
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integer i;
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begin
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set = 1'b0;
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ff1 = 'b0;
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for (i = 0; i < NUM_PORTS; i = i + 1) begin
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if (in[i] & ~set) begin
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set = 1'b1;
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ff1 = i[0 +: SEL_WIDTH];
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end
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end
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end
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endfunction
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`ifdef VERBOSE
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initial $display("Bus arbiter with %d units", NUM_PORTS);
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`endif
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/**
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* Internal signals
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*/
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integer yy;
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wire next;
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wire [NUM_PORTS-1:0] order;
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reg [NUM_PORTS-1:0] token;
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wire [NUM_PORTS-1:0] token_lookahead [NUM_PORTS-1:0];
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wire [WRAP_LENGTH-1:0] token_wrap;
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/**
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* Implementation
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*/
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assign token_wrap = {token, token};
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assign next = ~|(token & request);
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always @(posedge clk)
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grant <= token & request;
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always @(posedge clk)
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select <= ff1(token & request);
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always @(posedge clk)
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active <= |(token & request);
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always @(posedge clk)
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if (rst) token <= 'b1;
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else if (next) begin
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for (yy = 0; yy < NUM_PORTS; yy = yy + 1) begin : TOKEN_
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if (order[yy]) begin
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token <= token_lookahead[yy];
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end
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end
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end
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genvar xx;
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generate
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for (xx = 0; xx < NUM_PORTS; xx = xx + 1) begin : ORDER_
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assign token_lookahead[xx] = token_wrap[xx +: NUM_PORTS];
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assign order[xx] = |(token_lookahead[xx] & request);
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end
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endgenerate
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endmodule
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`endif // `ifndef _arbiter_
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101
cores/wb/wb_arbiter/rtl/wb_arbiter.v
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101
cores/wb/wb_arbiter/rtl/wb_arbiter.v
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/* wb_arbiter. Part of wb_intercon
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*
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* ISC License
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*
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* Copyright (C) 2013-2019 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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Wishbone arbiter, burst-compatible
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Simple round-robin arbiter for multiple Wishbone masters
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*/
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`include "clog2.vh"
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module wb_arbiter
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#(parameter dw = 32,
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parameter aw = 32,
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parameter num_hosts = 0,
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parameter num_masters = num_hosts)
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(
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input wire wb_clk_i,
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input wire wb_rst_i,
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// Wishbone Master Interface
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input wire [num_masters*aw-1:0] wbm_adr_i,
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input wire [num_masters*dw-1:0] wbm_dat_i,
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input wire [num_masters*4-1:0] wbm_sel_i,
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input wire [num_masters-1:0] wbm_we_i,
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input wire [num_masters-1:0] wbm_cyc_i,
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input wire [num_masters-1:0] wbm_stb_i,
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input wire [num_masters*3-1:0] wbm_cti_i,
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input wire [num_masters*2-1:0] wbm_bte_i,
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output wire [num_masters*dw-1:0] wbm_dat_o,
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output wire [num_masters-1:0] wbm_ack_o,
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output wire [num_masters-1:0] wbm_err_o,
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output wire [num_masters-1:0] wbm_rty_o,
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// Wishbone Slave interface
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output wire [aw-1:0] wbs_adr_o,
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output wire [dw-1:0] wbs_dat_o,
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output wire [3:0] wbs_sel_o,
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output wire wbs_we_o,
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output wire wbs_cyc_o,
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output wire wbs_stb_o,
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output wire [2:0] wbs_cti_o,
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output wire [1:0] wbs_bte_o,
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input wire [dw-1:0] wbs_dat_i,
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input wire wbs_ack_i,
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input wire wbs_err_i,
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input wire wbs_rty_i);
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///////////////////////////////////////////////////////////////////////////////
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// Parameters
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///////////////////////////////////////////////////////////////////////////////
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//Use parameter instead of localparam to work around a bug in Xilinx ISE
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parameter master_sel_bits = num_masters > 1 ? `CLOG2(num_masters) : 1;
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wire [num_masters-1:0] grant;
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wire [master_sel_bits-1:0] master_sel;
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wire active;
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arbiter
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#(.NUM_PORTS (num_masters))
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arbiter0
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(.clk (wb_clk_i),
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.rst (wb_rst_i),
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.request (wbm_cyc_i),
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.grant (grant),
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.select (master_sel),
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.active (active));
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/* verilator lint_off WIDTH */
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//Mux active master
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assign wbs_adr_o = wbm_adr_i[master_sel*aw+:aw];
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assign wbs_dat_o = wbm_dat_i[master_sel*dw+:dw];
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assign wbs_sel_o = wbm_sel_i[master_sel*4+:4];
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assign wbs_we_o = wbm_we_i [master_sel];
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assign wbs_cyc_o = wbm_cyc_i[master_sel] & active;
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assign wbs_stb_o = wbm_stb_i[master_sel];
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assign wbs_cti_o = wbm_cti_i[master_sel*3+:3];
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assign wbs_bte_o = wbm_bte_i[master_sel*2+:2];
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assign wbm_dat_o = {num_masters{wbs_dat_i}};
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assign wbm_ack_o = ((wbs_ack_i & active) << master_sel);
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assign wbm_err_o = ((wbs_err_i & active) << master_sel);
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assign wbm_rty_o = ((wbs_rty_i & active) << master_sel);
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/* verilator lint_on WIDTH */
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endmodule // wb_arbiter
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