Added everything from the other system

2026-02-28 21:46:59 +01:00
parent 907f244b24
commit cf483decad
34 changed files with 1601 additions and 57 deletions
--- a/cores/util/conv/conv.core
+++ b/cores/util/conv/conv.core
@@ -0,0 +1,16 @@
+CAPI=2:
+
+name: joppeb:util:conv:1.0
+description: Verilog conversion helper header
+
+filesets:
+    include:
+        files:
+            - conv.vh:
+                is_include_file: true
+        file_type: verilogSource
+
+targets:
+    default:
+        filesets:
+            - include