Added everything from the other system

cores/util/conv/conv.core

@@ -0,0 +1,16 @@
+CAPI=2:
+
+name: joppeb:util:conv:1.0
+description: Verilog conversion helper header
+
+filesets:
+    include:
+        files:
+            - conv.vh:
+                is_include_file: true
+        file_type: verilogSource
+
+targets:
+    default:
+        filesets:
+            - include

cores/util/conv/conv.vh

@@ -0,0 +1,16 @@
+`ifndef CONV_VH
+`define CONV_VH
+
+// =============================================================================
+// Convert Q1.15 to a biased UQ0.16 signal
+// =============================================================================
+function [15:0] q15_to_uq16;
+    input [15:0] q15;
+    reg [16:0] biased;
+begin
+    biased = q15 + 17'sd32768;
+    q15_to_uq16 = biased[15:0];
+end
+endfunction
+
+`endif