Added everything from the other system

This commit is contained in:
2026-02-28 21:46:59 +01:00
parent 907f244b24
commit cf483decad
34 changed files with 1601 additions and 57 deletions

View File

@@ -1,6 +1,8 @@
`timescale 1ns/1ps
module toplevel(
module toplevel #(
parameter sim = 0
)(
input wire aclk,
input wire aresetn,
@@ -11,6 +13,7 @@ module toplevel(
output wire[7:0] LED
);
`include "conv.vh"
// Clocking
wire clk_100;
@@ -25,56 +28,75 @@ module toplevel(
.clk_out(clk_15)
);
wire wb_rst;
assign wb_rst = ~aresetn;
wire [31:0] wb_adr;
wire [31:0] wb_dat_w;
wire [31:0] wb_dat_r;
wire [3:0] wb_sel;
wire wb_we;
wire wb_cyc;
wire wb_stb;
wire wb_ack;
wire wb_cmd_reset;
// Reset conditioning for button input:
// - asynchronous assert when button is pressed (aresetn=0)
// - synchronous, debounced deassert in clk_15 domain
localparam [17:0] RESET_RELEASE_CYCLES = sim ? 18'd16 : 18'd150000; // ~10 ms @ 15 MHz on hardware
reg [17:0] rst_cnt = 18'd0;
reg sys_reset_r = 1'b1;
always @(posedge clk_15 or negedge aresetn) begin
if (!aresetn) begin
rst_cnt <= 18'd0;
sys_reset_r <= 1'b1;
end else if (sys_reset_r) begin
if (rst_cnt == RESET_RELEASE_CYCLES - 1'b1)
sys_reset_r <= 1'b0;
else
rst_cnt <= rst_cnt + 1'b1;
end
end
wire sys_reset = sys_reset_r;
wire sys_resetn = !sys_reset_r;
wire [31:0] gpio_out;
wire gpio_rst;
assign gpio_rst = wb_rst;
wire [31:0] GPIO_A;
wire [31:0] GPIO_B;
wire [31:0] GPIO_C;
wire [31:0] GPIO_D;
jtag_wb_bridge u_jtag_wb_bridge (
wire test;
mcu #(
.memfile("../sw/sweep/sweep.hex"),
.sim(sim),
.jtag(1)
) mcu (
.i_clk(clk_15),
.i_rst(wb_rst),
.o_wb_adr(wb_adr),
.o_wb_dat(wb_dat_w),
.o_wb_sel(wb_sel),
.o_wb_we(wb_we),
.o_wb_cyc(wb_cyc),
.o_wb_stb(wb_stb),
.i_wb_rdt(wb_dat_r),
.i_wb_ack(wb_ack),
.o_cmd_reset(wb_cmd_reset)
.i_rst(sys_reset),
.i_GPI_A(GPIO_A),
.i_GPI_B(GPIO_B),
.i_GPI_C(GPIO_C),
.i_GPI_D(GPIO_D),
.o_GPO_A(GPIO_A),
.o_GPO_B(GPIO_B),
.o_GPO_C(GPIO_C),
.o_GPO_D(GPIO_D)
);
wb_gpio #(
.address(32'h00000000)
) u_wb_gpio (
.i_wb_clk(clk_15),
.i_wb_rst(gpio_rst),
.i_wb_adr(wb_adr),
.i_wb_dat(wb_dat_w),
.i_wb_sel(wb_sel),
.i_wb_we(wb_we),
.i_wb_stb(wb_cyc & wb_stb),
.i_gpio(gpio_out),
.o_wb_rdt(wb_dat_r),
.o_wb_ack(wb_ack),
.o_gpio(gpio_out)
wire [15:0] sin_q15;
wire clk_en;
nco_q15 #(
.CLK_HZ(15_000_000),
.FS_HZ(80_000)
) nco (
.clk (clk_15),
.rst_n (sys_resetn),
.freq_hz(GPIO_A),
.sin_q15(sin_q15),
.cos_q15(),
.clk_en (clk_en)
);
assign led_green = aresetn;
assign led_red = wb_cmd_reset;
assign LED = gpio_out[7:0];
assign r2r = gpio_out[13:8];
reg [5:0] dac_code;
always @(posedge clk_15) begin
dac_code <= q15_to_uq16(sin_q15) >> 10;
end
assign r2r = dac_code;
assign LED = GPIO_B[7:0];
assign led_green = GPIO_C[0];
assign led_red = GPIO_C[1];
endmodule