Added mul tb and fixed

2025-10-19 16:18:40 +02:00
parent eb7caaf2c5
commit b2858ac5ee
5 changed files with 136 additions and 17 deletions
--- a/project.cfg
+++ b/project.cfg
@@ -41,9 +41,11 @@ files_xco           = boards/mimas_v1/ip/clk_gen.xco
 [target.sim]
 toolchain           = iverilog
 runtime             = all
-toplevel            = tb_nco_q15
+toplevel            = tb_sigmadelta
 ivl_opts            = -Irtl/util
 files_verilog       = sim/tb/tb_nco_q15.v
+                      sim/tb/tb_sigmadelta.v
+                      sim/tb/tb_mul_const.v
                      rtl/core/nco_q15.v
                      rtl/core/lvds_comparator.v
                      rtl/core/sigmadelta_rcmodel_q15.v