Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem

sim/overrides/clk_gen.v

@@ -0,0 +1,15 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// Clock generator/PLL
+// Simple direct generation for simulation purposes
+// =============================================================================
+module clk_gen(
+    input wire clk_in,
+    output wire clk_out_15
+);
+    reg clk_15;
+    initial clk_15 <= 1'b0;
+    always #6.667 clk_15 <= !clk_15;
+    assign clk_out_15 = clk_15;
+endmodule

sim/tb/tb_mul_const.v

@@ -0,0 +1,72 @@
+`timescale 1ns/1ps
+
+module tb_mul_const();
+
+    // -------------------------------------------------------------------------
+    // Parameters
+    // -------------------------------------------------------------------------
+    localparam integer W = 16;
+    localparam integer C = 16'sh0B3B;   // alpha_q15 ≈ 0.08774
+    localparam signed [W-1:0] C_S = C[W-1:0];
+
+    // -------------------------------------------------------------------------
+    // DUT I/O
+    // -------------------------------------------------------------------------
+    reg  signed [W-1:0]     x;
+    wire signed [(2*W)-1:0] y;
+
+    // Instantiate DUT
+    mul_const_shiftadd #(
+        .W(W),
+        .C(C)
+    ) dut (
+        .x(x),
+        .y(y)
+    );
+
+    // -------------------------------------------------------------------------
+    // Reference and verification
+    // -------------------------------------------------------------------------
+    reg signed [(2*W)-1:0] expected;
+    integer i;
+    integer errors;
+
+    initial begin
+        $display("------------------------------------------------------");
+        $display(" Testbench: mul_const_shiftadd");
+        $display(" W = %0d, C = %0d (0x%0h)", W, $signed(C_S), C_S);
+        $display("------------------------------------------------------");
+
+        errors = 0;
+
+        // Exhaustively test all 16-bit signed values
+        for (i = -(1<<(W-1)); i < (1<<(W-1)); i = i + 1) begin
+            x = i;
+            #1; // let combinational logic settle
+
+            expected = $signed(x) * $signed(C_S);
+
+            if (y !== expected) begin
+                $display("FAIL: x=%6d (0x%04h) * C=%6d -> y=%10d (0x%08h), expected=%10d (0x%08h)",
+                         $signed(x), x, $signed(C_S),
+                         $signed(y), y, $signed(expected), expected);
+                errors = errors + 1;
+                // Uncomment next line if you want to stop on first mismatch
+                // $stop;
+            end
+
+            // progress message every 4096 iterations
+            if (((i + (1<<(W-1))) % 4096) == 0)
+                $display("Progress: %5d / %5d values tested...",
+                         i + (1<<(W-1)), (1<<W));
+        end
+
+        if (errors == 0)
+            $display("✅ PASS: All %0d test cases matched perfectly.", (1<<W));
+        else
+            $display("❌ FAIL: %0d mismatches found out of %0d cases.",
+                     errors, (1<<W));
+
+        $finish;
+    end
+endmodule

sim/tb/tb_sigmadelta.v

@@ -0,0 +1,36 @@
+`timescale 1ns/1ps
+
+module tb_sigmadelta();
+    // Clock and reset generation
+    reg clk;
+    reg resetn;
+    initial clk <= 1'b0;
+    initial resetn <= 1'b0;
+    always #6.667 clk <= !clk;
+    initial #40 resetn <= 1'b1;
+
+    // Default run
+    initial begin
+        $dumpfile("out.vcd");
+        $dumpvars;
+        #2_000_000
+        $finish;
+    end;
+
+    wire sd_a;
+    wire sd_b;
+    wire sd_o;
+    wire signed [15:0] decimated_q15;
+    wire decimated_valid;
+
+    sigmadelta_input #(
+        .R_OHM(3300),
+        .C_PF(220)
+    ) dut(
+        .clk_15(clk), .resetn(resetn),
+        .adc_a(sd_a), .adc_b(sd_b), .adc_o(sd_o),
+        .signal_q15(decimated_q15),
+        .signal_valid(decimated_valid)
+    );
+
+endmodule