Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem

rtl/core/clk_gen.v

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+`timescale 1ns/1ps
+
+// =============================================================================
+// Clock generator/PLL
+// Simple pass through
+// =============================================================================
+module clk_gen(
+    input wire clk_in,
+    output wire clk_out_15
+);
+   assign clk_out_15 = clk_in;
+endmodule

rtl/core/decimate_by_r_q15.v

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+`timescale 1ns/1ps
+
+// =============================================================================
+// Decimator by R
+// Reduces the effective sample rate by an integer factor R by selecting every
+// R-th input sample. Generates a one-cycle 'out_valid' pulse each time a new
+// decimated sample is produced.
+//
+// Implements:
+//      For each valid input sample:
+//          if (count == R-1):
+//              count     <= 0
+//              out_q15   <= in_q15
+//              out_valid <= 1
+//          else:
+//              count     <= count + 1
+//
+// parameters:
+//      -- R      : integer decimation factor (e.g., 400)
+//                   output sample rate = input rate / R
+//      -- CNT_W  : counter bit width, must satisfy 2^CNT_W > R
+//
+// inout:
+//      -- clk       : input clock (same rate as 'in_valid')
+//      -- rst_n     : active-low synchronous reset
+//      -- in_valid  : input data strobe; assert 1'b1 if input is always valid
+//      -- in_q15    : signed 16-bit Q1.15 input sample (full-rate)
+//      -- out_valid : single-cycle pulse every R samples (decimated rate strobe)
+//      -- out_q15   : signed 16-bit Q1.15 output sample (decimated stream)
+//
+// Notes:
+//  - This module performs *pure downsampling* (sample selection only).
+//    It does not include any anti-alias filtering; high-frequency content
+//    above the new Nyquist limit (Fs_out / 2) will alias into the baseband.
+//  - For most applications, an anti-alias low-pass filter such as
+//    lpf_iir_q15 or a FIR stage should precede this decimator.
+//  - The output sample rate is given by:
+//          Fs_out = Fs_in / R
+//  - Typical usage: interface between high-rate sigma-delta or oversampled
+//    data streams and lower-rate processing stages.
+// =============================================================================
+module decimate_by_r_q15 #(
+    parameter integer R      = 400, // decimation factor
+    parameter integer CNT_W  = 10   // width so that 2^CNT_W > R (e.g., 10 for 750)
+)(
+    input  wire        clk,
+    input  wire        rst_n,
+    input  wire        in_valid,          // assert 1'b1 if always valid
+    input  wire signed [15:0] in_q15,     // Q1.15 sample at full rate
+    output reg         out_valid,         // 1-cycle pulse every R samples
+    output reg  signed [15:0] out_q15     // Q1.15 sample at decimated rate
+);
+    reg [CNT_W-1:0] cnt;
+
+    always @(posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            cnt       <= {CNT_W{1'b0}};
+            out_valid <= 1'b0;
+            out_q15   <= 16'sd0;
+        end else begin
+            out_valid <= 1'b0;
+
+            if (in_valid) begin
+                if (cnt == R-1) begin
+                    cnt       <= {CNT_W{1'b0}};
+                    out_q15   <= in_q15;
+                    out_valid <= 1'b1;
+                end else begin
+                    cnt <= cnt + 1'b1;
+                end
+            end
+        end
+    end
+endmodule

rtl/core/lpf_iir_q15_k.v

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+`timescale 1ns/1ps
+
+// =============================================================================
+// Low-Pass IIR Filter (Q1.15)
+// Simple first-order infinite impulse response filter, equivalent to an
+// exponential moving average. Provides an adjustable smoothing factor based
+// on parameter K.
+//
+// Implements:
+//      Y[n+1] = Y[n] + (X[n] - Y[n]) / 2^K
+//
+// This is a purely digital one-pole low-pass filter whose time constant
+// approximates that of an analog RC filter, where alpha = 1 / 2^K.
+//
+// The larger K is, the slower the filter responds (stronger smoothing).
+// The smaller K is, the faster it reacts to changes.
+//
+// parameters:
+//      -- K : filter shift factor (integer, 4..14 typical)
+//              cutoff frequency ≈ Fs / (2π * 2^K)
+//              larger K → lower cutoff
+//
+// inout:
+//      -- clk   : input clock
+//      -- rst_n : active-low reset
+//      -- x_q15 : signed 16-bit Q1.15 input sample (e.g., 0..0x7FFF)
+//      -- y_q15 : signed 16-bit Q1.15 filtered output
+//
+// Notes:
+//  - The arithmetic right shift implements division by 2^K.
+//  - Internal arithmetic is Q1.15 fixed-point with saturation
+//    to [0, 0x7FFF] (for non-negative signals).
+//  - Useful for smoothing noisy ADC / sigma-delta data streams
+//    or modeling an RC envelope follower.
+// =============================================================================
+module lpf_iir_q15_k #( 
+    parameter integer K = 10 // try 8..12; bigger = more smoothing 
+)( 
+    input wire clk, 
+    input wire rst_n, 
+    input wire signed [15:0] x_q15, // Q1.15 input (e.g., 0..0x7FFF) 
+    output reg signed [15:0] y_q15 // Q1.15 output 
+); 
+    wire signed [15:0] e_q15 = x_q15 - y_q15; 
+    wire signed [15:0] delta_q15 = e_q15 >>> K; // arithmetic shift 
+    wire signed [15:0] y_next = y_q15 + delta_q15; // clamp to [0, 0x7FFF] (handy if your signal is non-negative) 
+    
+    function signed [15:0] clamp01; 
+        input signed [15:0] v; 
+    begin
+        if (v < 16'sd0) 
+            clamp01 = 16'sd0; 
+        else if (v > 16'sh7FFF) 
+            clamp01 = 16'sh7FFF; 
+        else 
+            clamp01 = v; 
+        end 
+    endfunction 
+    
+    always @(posedge clk or negedge rst_n) begin 
+        if (!rst_n) y_q15 <= 16'sd0; 
+        else y_q15 <= clamp01(y_next); 
+    end 
+endmodule

rtl/core/mul_const.v

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+`timescale 1ns/1ps
+
+// =============================================================================
+// Multiply a value by a constant
+// Use a shift-add algorithm instead of a multiplier
+// parameters:
+//      -- W : data width
+//      -- C : constant
+// inout:
+//      -- x : input of width W
+//      -- y : output of widht 2W
+// =============================================================================
+module mul_const_shiftadd#(
+    parameter integer W   = 16,
+    parameter integer C   = 16'sh7fff
+)(
+    input  wire signed [W-1:0] x,
+    output wire signed [2*W-1:0] y
+);
+    // Sign and magnitude of constant
+    localparam integer C_NEG = (C < 0) ? 1 : 0;
+    localparam integer C_ABS = (C < 0) ? -C : C;
+
+    // MSB index of |C| (0-based). Keeps network minimal.
+    function integer msb_index;
+        input integer v;
+        integer i;
+        begin
+            msb_index = -1;
+            for (i = 0; i < 32; i = i + 1)
+                if (v >> i) msb_index = i;
+        end
+    endfunction
+
+    localparam integer I_MAX = (C_ABS == 0) ? 0 : msb_index(C_ABS);
+
+    // Width big enough for the largest partial product: W bits shifted by I_MAX
+    localparam integer PPW = W + I_MAX + 1;
+
+    // Pre-extend x to PPW so shifts don’t truncate high/sign bits
+    wire signed [PPW-1:0] x_ext = {{(PPW-W){x[W-1]}}, x};
+
+    // Partial products (only where C’s bit is 1)
+    wire signed [PPW-1:0] part [0:I_MAX];
+    genvar i;
+    generate
+        for (i = 0; i <= I_MAX; i = i + 1) begin : GEN_PARTS
+            assign part[i] = C_ABS[i] ? (x_ext <<< i) : {PPW{1'b0}};
+        end
+    endgenerate
+
+    // Adder chain (you can replace with a balanced tree for speed)
+    wire signed [PPW-1:0] sum [0:I_MAX];
+    generate
+        if (I_MAX == 0) begin
+            assign sum[0] = part[0];
+        end else begin
+            assign sum[0] = part[0];
+            for (i = 1; i <= I_MAX; i = i + 1) begin : GEN_SUM
+                assign sum[i] = sum[i-1] + part[i];
+            end
+        end
+    endgenerate
+
+    // Apply sign of C
+    wire signed [PPW-1:0] mag  = (I_MAX == 0) ? part[0] : sum[I_MAX];
+    wire signed [PPW-1:0] prod = C_NEG ? -mag : mag;
+
+    // Stretch/extend to 2W result width
+    assign y = {{((2*W)-PPW){prod[PPW-1]}}, prod};
+endmodule

rtl/core/sigmadelta_input_q15.v

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+`timescale 1ns/1ps
+
+module sigmadelta_input #(
+    parameter integer R_OHM = 3300,
+    parameter integer C_PF = 220
+)(
+    input wire clk_15,
+    input wire resetn,
+    
+    input wire adc_a,
+    input wire adc_b,
+    output wire adc_o,
+
+    output wire signed [15:0] signal_q15,
+    output wire signal_valid
+);
+    `include "rc_alpha_q15.vh"
+
+    wire sd_signal;
+    wire signed [15:0] raw_sample_q15;
+    wire signed [15:0] lpf_sample_q15;
+
+    sigmadelta_sampler sd_sampler(
+        .clk(clk_15),
+        .a(adc_a), .b(adc_b),
+        .o(sd_signal)
+    );
+    assign adc_o = sd_signal;
+
+    localparam integer alpha_q15_int = alpha_q15_from_rc(R_OHM, C_PF, 15000000);
+    localparam signed [15:0] alpha_q15 = alpha_q15_int[15:0];
+    localparam signed [15:0] alpha_q15_top = alpha_q15 & 16'hff00;
+    sigmadelta_rcmodel_q15 #(
+        .alpha_q15(alpha_q15_top)
+    ) rc_model (
+        .clk(clk_15), .resetn(resetn),
+        .sd_sample(sd_signal),
+        .sample_q15(raw_sample_q15)
+    );
+
+    lpf_iir_q15_k #(
+        .K(10)
+    ) lpf (
+        .clk(clk_15), .rst_n(resetn),
+        .x_q15(raw_sample_q15),
+        .y_q15(lpf_sample_q15)
+    );
+
+    decimate_by_r_q15 #(
+        .R(375), // 15MHz/375 = 40KHz
+        .CNT_W(10)
+    ) decimate (
+        .clk(clk_15), .rst_n(resetn),
+        .in_valid(1'b1), .in_q15(lpf_sample_q15),
+        .out_valid(signal_valid), .out_q15(signal_q15)
+    );
+
+endmodule

rtl/core/sigmadelta_rcmodel_q15.v

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+`timescale 1ns/1ps
+
+// =============================================================================
+// RC model to convert sigma delta samples to Q1.15
+// Models the RC circuit on the outside of the FPGA
+// Uses: Yn+1 = Yn + (sd - Yn)*(1-exp(-T/RC))
+// parameters:
+//      -- alpha_q15 : the 1-exp(-T/RC), defaults to R=3k3, C=220p and T=1/15MHz
+//							  rounded to only use two bits (0b3b -> 0b00), the less
+//							  bits the better
+// inout:
+//      -- clk : input clock
+//      -- resetn : reset signal
+//      -- sd_sample : 1 bit sample output from sd sampler
+//      -- sample_q15 : output samples in q.15
+// =============================================================================
+module sigmadelta_rcmodel_q15 #(
+    parameter integer alpha_q15 = 16'sh0b00
+)(
+    input wire clk,
+    input wire resetn,
+    input wire sd_sample,
+    output wire [15:0] sample_q15
+);
+    reg signed [15:0] y_q15;
+    wire signed [15:0] sd_q15 = sd_sample ? 16'sh7fff : 16'sh0000;
+    wire signed [15:0] e_q15 = sd_q15 - y_q15;
+    // wire signed [31:0] prod_q30 = $signed(e_q15) * $signed(alpha_q15);
+    wire signed [31:0] prod_q30;
+    // Use shift-add algorithm for multiplication
+    mul_const_shiftadd #(.C($signed(alpha_q15))) alpha_times_e ($signed(e_q15), prod_q30);
+    wire signed [15:0] y_next_q15 = y_q15 + (prod_q30>>>15);
+
+    // clamp to [0, 0x7FFF] (keeps signal view tidy)
+    function signed [15:0] clamp01_q15(input signed [15:0] v);
+        if (v < 16'sd0000) clamp01_q15 = 16'sd0000;
+        else if (v > 16'sh7FFF) clamp01_q15 = 16'sh7FFF;
+        else clamp01_q15 = v;
+    endfunction
+
+    always @(posedge clk or negedge resetn) begin
+        if (!resetn) y_q15 <= 16'sd0000;
+        else y_q15 <= clamp01_q15(y_next_q15);
+    end
+
+    assign sample_q15 = y_q15;
+
+endmodule