joppe/fpga_modem
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Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem

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This commit is contained in:
Joppe Blondel
2026-02-22 16:07:34 +01:00
parent dc946cd793 49b8a77480
commit ac6aea90b6
17 changed files with 1004 additions and 17 deletions
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44
project.cfg
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@@ -19,21 +19,29 @@ device = xc6slx9
package = tqg144
speedgrade = -2
toplevel = top_generic
xst_opts = -vlgincdir rtl
#ngdbuild_opts =
#map_opts =
#par_opts =
#netgen_opts =
#bitgen_opts =
#trce_opts =
# Files
#files_vhdl =
xst_opts = -vlgincdir rtl/util
files_verilog = rtl/toplevel/top_generic.v
rtl/core/nco_q15.v
rtl/core/sigmadelta_sampler.v
rtl/core/sigmadelta_rcmodel_q15.v
rtl/core/sigmadelta_input_q15.v
rtl/core/mul_const.v
rtl/core/lpf_iir_q15_k.v
rtl/core/decimate_by_r_q15.v
rtl/arch/spartan-6/lvds_comparator.v
rtl/arch/spartan-6/clk_gen.v
files_con = boards/mimas_v1/constraints.ucf
files_other = rtl/util/conv.vh
rtl/util/rc_alpha_q15.vh
[target.ip]
toolchain = ISE_IP
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
files_xco = boards/mimas_v1/ip/clk_gen.xco
[target.serv]
toolchain = ISE
@@ -78,13 +86,19 @@ files_verilog = rtl/util/clog2.vh
[target.sim]
toolchain = iverilog
runtime = all
toplevel = tb_nco_q15
ivl_opts = -Irtl
#vvp_opts =
# Files
#files_sysverilog =
toplevel = tb_sigmadelta
ivl_opts = -Irtl/util
files_verilog = sim/tb/tb_nco_q15.v
sim/tb/tb_sigmadelta.v
sim/tb/tb_mul_const.v
rtl/core/nco_q15.v
rtl/core/lvds_comparator.v
rtl/core/sigmadelta_rcmodel_q15.v
rtl/core/sigmadelta_input_q15.v
rtl/core/mul_const.v
rtl/core/lpf_iir_q15_k.v
rtl/core/decimate_by_r_q15.v
sim/overrides/sigmadelta_sampler.v
files_other = rtl/util/conv.vh
sim/overrides/clk_gen.v
files_other = rtl/util/conv.vh
rtl/util/rc_alpha_q15.vh