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This commit is contained in:
Joppe Blondel
2026-03-01 17:16:44 +01:00
parent 7b46ae5e87
commit abe0668787
19 changed files with 381 additions and 155 deletions
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91
cores/wb/check_formal.sh
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@@ -1,91 +0,0 @@
#!/bin/sh
# Add or remove cores here. Each entry should be a full FuseSoC VLNV.
CORES="
joppeb:wb:wb_mem32
joppeb:wb:wb_gpio
joppeb:wb:wb_gpio_banks
joppeb:wb:jtag_wb_bridge
joppeb:wb:wb_timer
"
# Add or remove formal tasks here.
TASKS="
bmc
cover
prove
"
total=0
passed=0
failed=0
passed_runs=""
failed_runs=""
run_task() {
core="$1"
task="$2"
label="$core [$task]"
log_file=""
total=$((total + 1))
printf '\n[%d] Running formal %s for %s\n' "$total" "$task" "$core"
log_file=$(mktemp /tmp/check_formal.XXXXXX) || exit 2
if \
FUSESOC_CORE="$core" \
FUSESOC_TASK="$task" \
script -qefc 'fusesoc run --target formal "$FUSESOC_CORE" --taskname "$FUSESOC_TASK"' "$log_file" \
>/dev/null 2>&1
then
passed=$((passed + 1))
passed_runs="$passed_runs
$label"
printf 'Result: PASS (%s)\n' "$label"
rm -f "$log_file"
return 0
else
failed=$((failed + 1))
failed_runs="$failed_runs
$label"
printf 'Result: FAIL (%s)\n' "$label"
printf 'Captured log for %s:\n' "$label"
cat "$log_file" | grep summary
rm -f "$log_file"
return 1
fi
}
for core in $CORES; do
for task in $TASKS; do
run_task "$core" "$task"
done
done
printf '\nFormal run summary\n'
printf ' Total: %d\n' "$total"
printf ' Passed: %d\n' "$passed"
printf ' Failed: %d\n' "$failed"
if [ -n "$passed_runs" ]; then
printf '\nPassed runs:\n'
printf '%s\n' "$passed_runs" | while IFS= read -r run; do
if [ -n "$run" ]; then
printf ' - %s\n' "$run"
fi
done
fi
if [ -n "$failed_runs" ]; then
printf '\nFailed runs:\n'
printf '%s\n' "$failed_runs" | while IFS= read -r run; do
if [ -n "$run" ]; then
printf ' - %s\n' "$run"
fi
done
fi
if [ "$failed" -ne 0 ]; then
exit 1
fi

56
cores/wb/formal_checker/formal/formal_wb_master_checker.v
View File

@@ -22,14 +22,14 @@ module formal_wb_master_checker (
// A1: Slave ACK must correspond to either a same-cycle or previous-cycle request
if(o_wb_ack)
assume(
A1: assume(
(i_wb_cyc && i_wb_stb) ||
(f_past_valid && $past(i_wb_cyc && i_wb_stb))
);
// A2: Slave must not ACK outside an active cycle
if(!i_wb_cyc)
assume(!o_wb_ack);
A2: assume(!o_wb_ack);
// A3: Once STB has been low for a full cycle, slave ACK must be low
if(
@@ -37,19 +37,19 @@ module formal_wb_master_checker (
!$past(i_wb_stb) &&
!i_wb_stb
)
assume(!o_wb_ack);
A3: assume(!o_wb_ack);
// R1: Reset must leave the master initialized on the following cycle
if(f_past_valid && $past(i_rst || i_wb_rst)) begin
assert(!i_wb_cyc);
assert(!i_wb_stb);
R1: assert(!i_wb_cyc);
R2: assert(!i_wb_stb);
end
// R2: STB never high without CYC
// R3: STB never high without CYC
if(i_wb_stb)
assert(i_wb_cyc);
R3: assert(i_wb_cyc);
// R3: Once a request starts, hold it stable until the slave responds
// R4-R9: Once a request starts, hold it stable until the slave responds
if(
f_past_valid &&
!$past(i_rst || i_wb_rst) &&
@@ -57,40 +57,40 @@ module formal_wb_master_checker (
!o_wb_ack &&
!(i_rst || i_wb_rst)
) begin
assert(i_wb_cyc);
assert(i_wb_stb);
assert(i_wb_adr == $past(i_wb_adr));
assert(i_wb_dat == $past(i_wb_dat));
assert(i_wb_sel == $past(i_wb_sel));
assert(i_wb_we == $past(i_wb_we));
R4: assert(i_wb_cyc);
R5: assert(i_wb_stb);
R6: assert(i_wb_adr == $past(i_wb_adr));
R7: assert(i_wb_dat == $past(i_wb_dat));
R8: assert(i_wb_sel == $past(i_wb_sel));
R9: assert(i_wb_we == $past(i_wb_we));
end
// R4: Once CYC is low, STB must also be low
// R10: Once CYC is low, STB must also be low
if(!i_wb_cyc)
assert(!i_wb_stb);
R10: assert(!i_wb_stb);
// C0: We eventually initiate a request
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb);
// C1: We eventually initiate a request
C1: cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb);
// C1: We eventually get an ACK during an active request
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && o_wb_ack);
// C2: We eventually get an ACK during an active request
C2: cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && o_wb_ack);
// C2: A delayed ACK occurs for a request issued in a previous cycle.
// C3: A delayed ACK occurs for a request issued in a previous cycle.
// This does not require the request to drop in the ACK cycle.
cover(f_past_valid && !i_rst && !i_wb_rst &&
C3: cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb) && o_wb_ack);
// C4: A “wait state” happens: request asserted, no ACK for at least 1 cycle
cover(f_past_valid && !i_rst && !i_wb_rst &&
C4: cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb && !o_wb_ack) &&
(i_wb_cyc && i_wb_stb && !o_wb_ack));
// C5: Read and write both occur (even if only once each)
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && !i_wb_we);
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && i_wb_we);
// C5-C6: Read and write both occur (even if only once each)
C5: cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && !i_wb_we);
C6: cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && i_wb_we);
// C6: A transfer completes and the master drops CYC sometime after
cover(f_past_valid && !i_rst && !i_wb_rst &&
// C7: A transfer completes and the master drops CYC sometime after
C7: cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb && o_wb_ack) && !i_wb_cyc);
end

66
cores/wb/formal_checker/formal/formal_wb_slave_checker.v
View File

@@ -1,7 +1,8 @@
`timescale 1ns/1ps
module formal_wb_slave_checker #(
parameter combinatorial_ack = 0
parameter combinatorial_ack = 0,
parameter expect_wait_state = 0
) (
input wire i_clk,
input wire i_rst,
@@ -24,38 +25,38 @@ module formal_wb_slave_checker #(
// A1: Reset forces cyc=0, stb=0
if (i_rst) begin
assume(!i_wb_cyc);
assume(!i_wb_stb);
A1: assume(!i_wb_cyc);
A2: assume(!i_wb_stb);
end
// A2: std->cyc, stb never high without cyc
// A3: std->cyc, stb never high without cyc
if(i_wb_stb)
assume(i_wb_cyc);
A3: assume(i_wb_cyc);
// A3: once a request starts, hold it stable until the slave responds
// A4-A9: once a request starts, hold it stable until the slave responds
if(f_past_valid && $past(i_wb_cyc && i_wb_stb && !o_wb_ack)) begin
assume(i_wb_cyc);
assume(i_wb_stb);
assume(i_wb_adr == $past(i_wb_adr));
assume(i_wb_dat == $past(i_wb_dat));
assume(i_wb_sel == $past(i_wb_sel));
assume(i_wb_we == $past(i_wb_we));
A4: assume(i_wb_cyc);
A5: assume(i_wb_stb);
A6: assume(i_wb_adr == $past(i_wb_adr));
A7: assume(i_wb_dat == $past(i_wb_dat));
A8: assume(i_wb_sel == $past(i_wb_sel));
A9: assume(i_wb_we == $past(i_wb_we));
end
// R1: ACK must correspond to either a same-cycle or previous-cycle request
if(o_wb_ack)
assert(
R1: assert(
(i_wb_cyc && i_wb_stb) ||
(f_past_valid && $past(i_wb_cyc && i_wb_stb))
);
// R2: !CYC->!ACK : no ghost acks
if(!i_wb_cyc)
assert(!o_wb_ack);
R2: assert(!o_wb_ack);
// R3: Reset must leave the slave initialized on the following cycle
if(f_past_valid && $past(i_rst || i_wb_rst))
assert(!o_wb_ack);
R3: assert(!o_wb_ack);
// R4: once STB has been dropped for a full cycle, ACK must be low
if(
@@ -63,34 +64,35 @@ module formal_wb_slave_checker #(
!$past(i_wb_stb) &&
!i_wb_stb
)
assert(!o_wb_ack);
R4: assert(!o_wb_ack);
// C0: A request occurs at all
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb);
// C1: A request occurs at all
C1: cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb);
// C1: A request with write and with read occur
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && i_wb_we);
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && !i_wb_we);
// C2-C3: A request with write and with read occur
C2: cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && i_wb_we);
C3: cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && !i_wb_we);
// C2: ACK happens during a request (basic progress)
cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && o_wb_ack);
// C4: ACK happens during a request (basic progress)
C4: cover(f_past_valid && !i_rst && !i_wb_rst && i_wb_cyc && i_wb_stb && o_wb_ack);
// C3: Exercise the expected ACK timing style for this slave.
// C5-C7: Exercise the expected ACK timing style for this slave.
if (combinatorial_ack) begin
cover(f_past_valid && !i_rst && !i_wb_rst &&
C5: cover(f_past_valid && !i_rst && !i_wb_rst &&
(i_wb_cyc && i_wb_stb) && o_wb_ack);
end else begin
cover(f_past_valid && !i_rst && !i_wb_rst &&
C6: cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb) && o_wb_ack);
// C4: Wait-state behavior for registered/non-zero-wait slaves.
cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb && !o_wb_ack) &&
(i_wb_cyc && i_wb_stb && !o_wb_ack));
// C7: Optional wait-state behavior for slaves that intentionally stall.
if (expect_wait_state)
C7: cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb && !o_wb_ack) &&
(i_wb_cyc && i_wb_stb && !o_wb_ack));
end
// C5: Master ends a cycle (CYC drops) after at least one request
cover(f_past_valid && !i_rst && !i_wb_rst &&
// C8: Master ends a cycle (CYC drops) after at least one request
C8: cover(f_past_valid && !i_rst && !i_wb_rst &&
$past(i_wb_cyc && i_wb_stb) && !i_wb_cyc);
end

13
cores/wb/wb_gpio/formal/wb_gpio/config.sby
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@@ -1,13 +0,0 @@
[options]
mode prove
depth 8
[engines]
smtbmc z3 parallel.enable=true parallel.threads.max=8
[script]
{{"-formal"|gen_reads}}
prep -top {{top_level}}
[files]
{{files}}

2
cores/wb/wb_gpio/formal/wb_gpio/logfile.txt
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@@ -1,2 +0,0 @@
SBY 17:32:33 [cores/wb/wb_gpio/formal/wb_gpio] Removing directory '/data/joppe/projects/fusesoc_test/cores/wb/wb_gpio/formal/wb_gpio'.
SBY 17:32:33 [cores/wb/wb_gpio/formal/wb_gpio] Copy '/data/joppe/projects/fusesoc_test/{{files}}' to '/data/joppe/projects/fusesoc_test/cores/wb/wb_gpio/formal/wb_gpio/src/{{files}}'.

14
cores/wb/wb_timer/formal/formal_wb_timer.v
View File

@@ -1,9 +1,6 @@
`timescale 1ns/1ps
module formal_wb_timer #(
parameter WIDTH = 8,
parameter DIVIDER = 0
);
module formal_wb_timer;
(* gclk *) reg i_clk;
(* anyseq *) reg i_rst;
(* anyseq *) reg [31:0] i_wb_adr;
@@ -20,15 +17,14 @@ module formal_wb_timer #(
assign i_wb_rst = 1'b0;
wb_countdown_timer #(
.WIDTH(WIDTH),
.DIVIDER(DIVIDER)
) dut (
wb_countdown_timer dut (
.i_clk(i_clk),
.i_rst(i_rst),
.o_irq(o_irq),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.o_wb_dat(o_wb_dat),
.i_wb_sel(i_wb_sel),
.i_wb_we(i_wb_we),
.i_wb_cyc(i_wb_cyc),
.i_wb_stb(i_wb_stb),
@@ -36,7 +32,7 @@ module formal_wb_timer #(
);
formal_wb_slave_checker #(
.combinatorial_ack(1)
.combinatorial_ack(0)
) wb_checker (
.i_clk(i_clk),
.i_rst(i_rst),

2
cores/wb/wb_timer/formal/wb_timer.sby
View File

@@ -13,7 +13,7 @@ prove: mode prove
[engines]
bmc: smtbmc yices
cover: smtbmc yices
prove: abc pdr
prove: smtbmc yices
[script]
{{"-formal"|gen_reads}}

118
cores/wb/wb_timer/rtl/wb_timer.v
View File

@@ -1,74 +1,100 @@
`timescale 1ns/1ps
module wb_countdown_timer #(
parameter WIDTH = 32, // counter width (<=32 makes bus mapping easy)
parameter DIVIDER = 0 // optional prescaler: tick every 2^DIVIDER cycles
parameter address = 32'h00000000 // Base address of peripheral
)(
input wire i_clk,
input wire i_rst,
output reg o_irq,
output wire o_irq,
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
output reg [31:0] o_wb_dat,
input wire [3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output wire o_wb_ack
);
// One-cycle acknowledge on any valid WB access
// (classic, zero-wait-state peripheral)
assign o_wb_ack = i_wb_cyc & i_wb_stb;
// Registers
reg [31:0] counter; // The actual counter. Generates an interrupt when it reaches 0
reg [31:0] preload; // The value with which the counter gets loaded after it reaches 0. 0 to keep the timer off
// Internal countdown and prescaler
reg [WIDTH-1:0] counter;
reg [DIVIDER:0] presc; // enough bits to count up to 2^DIVIDER-1
wire tick = (DIVIDER == 0) ? 1'b1 : (presc[DIVIDER] == 1'b1);
reg wb_ack = 0;
reg irq_fired = 0;
reg counter_started = 0;
reg counter_running = 0;
reg prev_counter_running = 0;
assign o_wb_ack = wb_ack;
// Readback: expose the current counter value
always @(*) begin
o_wb_dat = 32'd0;
o_wb_dat[WIDTH-1:0] = counter;
end
assign o_irq = irq_fired;
// Main logic
always @(posedge i_clk) begin
if (i_rst) begin
counter <= {WIDTH{1'b0}};
presc <= { (DIVIDER+1){1'b0} };
o_irq <= 1'b0;
if(i_rst) begin
counter <= 0;
preload <= 0;
wb_ack <= 0;
o_wb_dat <= 0;
irq_fired <= 0;
counter_started <= 0;
counter_running <= 0;
prev_counter_running <= 0;
end else begin
// Default prescaler behavior
if (DIVIDER != 0) begin
if (counter != 0 && !o_irq)
presc <= presc + 1'b1;
else
presc <= { (DIVIDER+1){1'b0} };
end
// Wishbone write: load counter and clear IRQ
if (o_wb_ack && i_wb_we) begin
counter <= i_wb_dat[WIDTH-1:0];
o_irq <= 1'b0;
prev_counter_running <= counter_running;
counter_running <= counter>0;
// reset prescaler on (re)start or stop
presc <= { (DIVIDER+1){1'b0} };
if(!irq_fired && prev_counter_running && !counter_running)
irq_fired <= 1'b1;
if(counter>0 && counter_started)
counter <= counter - 1;
end else begin
// Countdown when running (counter>0), not already IRQ'd
if (!o_irq && counter != 0) begin
if (tick) begin
if (counter == 1) begin
counter <= {WIDTH{1'b0}};
o_irq <= 1'b1; // sticky until next write
presc <= { (DIVIDER+1){1'b0} };
end else begin
counter <= counter - 1'b1;
end
end
if(counter == 0 && preload>0 && counter_started)
counter <= preload;
if(counter == 0 && preload == 0)
counter_started <= 1'b0;
// Ack generation
wb_ack <= i_wb_cyc & i_wb_stb & !wb_ack;
// Read cycle
if(i_wb_cyc && i_wb_stb && !i_wb_we) begin
if(i_wb_adr[3:0] == 4'b0000) begin
if(i_wb_sel[0]) o_wb_dat[7:0] <= counter[7:0];
if(i_wb_sel[1]) o_wb_dat[15:8] <= counter[15:8];
if(i_wb_sel[2]) o_wb_dat[23:16] <= counter[23:16];
if(i_wb_sel[3]) o_wb_dat[31:24] <= counter[31:24];
end else if(i_wb_adr[3:0] == 4'b0100) begin
if(i_wb_sel[0]) o_wb_dat[7:0] <= preload[7:0];
if(i_wb_sel[1]) o_wb_dat[15:8] <= preload[15:8];
if(i_wb_sel[2]) o_wb_dat[23:16] <= preload[23:16];
if(i_wb_sel[3]) o_wb_dat[31:24] <= preload[31:24];
end
end
// write cycle
if(i_wb_cyc && i_wb_stb && i_wb_we) begin
if(i_wb_adr[3:0] == 4'b0000) begin
if(i_wb_sel[0]) counter[7:0] <= i_wb_dat[7:0];
if(i_wb_sel[1]) counter[15:8] <= i_wb_dat[15:8];
if(i_wb_sel[2]) counter[23:16] <= i_wb_dat[23:16];
if(i_wb_sel[3]) counter[31:24] <= i_wb_dat[31:24];
counter_started <= 1'b1;
end else if(i_wb_adr[3:0] == 4'b0100) begin
if(i_wb_sel[0]) preload[7:0] <= i_wb_dat[7:0];
if(i_wb_sel[1]) preload[15:8] <= i_wb_dat[15:8];
if(i_wb_sel[2]) preload[23:16] <= i_wb_dat[23:16];
if(i_wb_sel[3]) preload[31:24] <= i_wb_dat[31:24];
counter_started <= 1'b1;
end else if(i_wb_adr[3:0] == 4'b1000) begin
// Any write to BASE+8 will ack the IRQ
irq_fired <= 1'b0;
end
end
end
end
endmodule
endmodule

143
cores/wb/wb_timer/tb/tb_wb_timer.v Normal file
View File

@@ -0,0 +1,143 @@
`timescale 1ns/1ps
module tb_wb_timer;
localparam ADDR_COUNTER = 32'h0000_0000;
localparam ADDR_PRELOAD = 32'h0000_0004;
localparam ADDR_ACK = 32'h0000_0008;
reg i_clk;
reg i_rst;
reg [31:0] i_wb_adr;
reg [31:0] i_wb_dat;
reg [3:0] i_wb_sel;
reg i_wb_we;
reg i_wb_stb;
reg i_wb_cyc;
wire [31:0] o_wb_dat;
wire o_wb_ack;
wire o_irq;
reg [31:0] read_data;
integer cycle;
wb_countdown_timer dut (
.i_clk(i_clk),
.i_rst(i_rst),
.o_irq(o_irq),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.o_wb_dat(o_wb_dat),
.i_wb_sel(i_wb_sel),
.i_wb_we(i_wb_we),
.i_wb_cyc(i_wb_cyc),
.i_wb_stb(i_wb_stb),
.o_wb_ack(o_wb_ack)
);
initial i_clk = 1'b0;
always #5 i_clk = ~i_clk;
task automatic wb_write;
input [31:0] addr;
input [31:0] data;
input [3:0] sel;
begin
@(negedge i_clk);
i_wb_adr <= addr;
i_wb_dat <= data;
i_wb_sel <= sel;
i_wb_we <= 1'b1;
i_wb_stb <= 1'b1;
i_wb_cyc <= 1'b1;
while (!o_wb_ack)
@(posedge i_clk);
@(negedge i_clk);
i_wb_we <= 1'b0;
i_wb_stb <= 1'b0;
i_wb_cyc <= 1'b0;
i_wb_sel <= 4'b0000;
i_wb_dat <= 32'h0000_0000;
end
endtask
task automatic wb_read;
input [31:0] addr;
output [31:0] data;
begin
@(negedge i_clk);
i_wb_adr <= addr;
i_wb_dat <= 32'h0000_0000;
i_wb_sel <= 4'b1111;
i_wb_we <= 1'b0;
i_wb_stb <= 1'b1;
i_wb_cyc <= 1'b1;
while (!o_wb_ack)
@(posedge i_clk);
#1;
data = o_wb_dat;
@(negedge i_clk);
i_wb_stb <= 1'b0;
i_wb_cyc <= 1'b0;
i_wb_sel <= 4'b0000;
end
endtask
initial begin
$dumpfile("wb_timer.vcd");
$dumpvars(0, tb_wb_timer);
i_rst = 1'b1;
i_wb_adr = 32'h0000_0000;
i_wb_dat = 32'h0000_0000;
i_wb_sel = 4'b0000;
i_wb_we = 1'b0;
i_wb_stb = 1'b0;
i_wb_cyc = 1'b0;
repeat (2) @(posedge i_clk);
i_rst = 1'b0;
wb_write(ADDR_COUNTER, 5, 4'b1111);
wb_write(ADDR_PRELOAD, 0, 4'b1111);
for (cycle = 0; cycle < 40; cycle = cycle + 1) begin
@(posedge i_clk);
if(o_irq)
wb_write(ADDR_ACK, 32'h0000_ffff, 4'b1111);
end
for (cycle = 0; cycle < 8; cycle = cycle + 1)
@(posedge i_clk);
wb_write(ADDR_PRELOAD, 8, 4'b1111);
for (cycle = 0; cycle < 21; cycle = cycle + 1) begin
@(posedge i_clk);
if(o_irq)
wb_write(ADDR_ACK, 32'h0000_ffff, 4'b1111);
end
wb_write(ADDR_PRELOAD, 6, 4'b1111);
for (cycle = 0; cycle < 21; cycle = cycle + 1) begin
@(posedge i_clk);
if(o_irq)
wb_write(ADDR_ACK, 32'h0000_ffff, 4'b1111);
end
wb_write(ADDR_PRELOAD, 0, 4'b1111);
for (cycle = 0; cycle < 10; cycle = cycle + 1) begin
@(posedge i_clk);
if(o_irq)
wb_write(ADDR_ACK, 32'h0000_ffff, 4'b1111);
end
$finish;
end
endmodule

24
cores/wb/wb_timer/wb_timer.core
View File

@@ -8,6 +8,10 @@ filesets:
files:
- rtl/wb_timer.v
file_type: verilogSource
tb:
files:
- tb/tb_wb_timer.v
file_type: verilogSource
formal_rtl:
depend:
- joppeb:wb:formal_checker
@@ -25,8 +29,13 @@ targets:
- rtl
toplevel: wb_countdown_timer
parameters:
- WIDTH
- DIVIDER
- address
sim:
default_tool: icarus
filesets:
- rtl
- tb
toplevel: tb_wb_timer
formal:
default_tool: symbiyosys
filesets:
@@ -35,15 +44,10 @@ targets:
- formal_cfg
toplevel: formal_wb_timer
parameters:
- WIDTH
- DIVIDER
- address
parameters:
WIDTH:
address:
datatype: int
description: Counter width in bits
paramtype: vlogparam
DIVIDER:
datatype: int
description: Prescaler divider as a power of two exponent
description: Base address of register set
paramtype: vlogparam