new timer

cores/system/test/tb/tb_toplevel.v

@@ -0,0 +1,37 @@
+`timescale 1ns/1ps
+
+module tb_toplevel;
+    reg        aclk;
+    reg        aresetn;
+    wire       led_green;
+    wire       led_red;
+    wire [5:0] r2r;
+    wire [7:0] LED;
+
+    toplevel #(
+        .sim(1)
+    ) dut (
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .led_green(led_green),
+        .led_red(led_red),
+        .r2r(r2r),
+        .LED(LED)
+    );
+
+    initial aclk = 1'b0;
+    always #33.33 aclk = ~aclk;
+
+    initial begin
+        $dumpfile("toplevel.vcd");
+        $dumpvars(1, tb_toplevel);
+
+        aresetn = 1'b0;
+        #100;
+        aresetn = 1'b1;
+
+        #10_000_000;
+
+        $finish;
+    end
+endmodule