new timer

2026-03-01 17:16:44 +01:00
parent 7b46ae5e87
commit abe0668787
19 changed files with 381 additions and 155 deletions
--- a/cores/system/test/rtl/toplevel.v
+++ b/cores/system/test/rtl/toplevel.v
@@ -1,7 +1,8 @@
 `timescale 1ns/1ps

 module toplevel #(
-    parameter sim = 0
+    parameter sim = 0,
+    parameter memfile = "sweep.hex"
 )(
    input wire aclk,
    input wire aresetn,
@@ -57,7 +58,7 @@ module toplevel #(
    wire test;

    mcu #(
-        .memfile("../sw/sweep/sweep.hex"),
+        .memfile(memfile),
        .sim(sim),
        .jtag(1)
    ) mcu (