joppe/fpga_modem
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This commit is contained in:
Joppe Blondel
2026-03-01 17:16:44 +01:00
parent 7b46ae5e87
commit abe0668787
19 changed files with 381 additions and 155 deletions
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8
cores/system/mcu/rtl/mcu_peripherals.v
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@@ -44,7 +44,9 @@ module mcu_peripherals (
wire [31:0] gpio_wbs_dat_r;
wire gpio_wbs_ack;
wire [31:0] timer_wbs_adr = wbs_adr[1*32 +: 32];
wire [31:0] timer_wbs_dat_w = wbs_dat_w[1*32 +: 32];
wire [3:0] timer_wbs_sel = wbs_sel[1*4 +: 4];
wire timer_wbs_we = wbs_we[1];
wire timer_wbs_cyc = wbs_cyc[1];
wire timer_wbs_stb = wbs_stb[1];
@@ -108,12 +110,16 @@ module mcu_peripherals (
assign wbs_dat_r[0*32 +: 32] = gpio_wbs_dat_r;
assign wbs_ack[0] = gpio_wbs_ack;
wb_countdown_timer timer (
wb_countdown_timer #(
.address(TIMER_BASE_ADDR)
) timer (
.i_clk(i_clk),
.i_rst(i_rst),
.o_irq(o_timer_irq),
.i_wb_adr(timer_wbs_adr),
.i_wb_dat(timer_wbs_dat_w),
.o_wb_dat(timer_wbs_dat_r),
.i_wb_sel(timer_wbs_sel),
.i_wb_we(timer_wbs_we),
.i_wb_cyc(timer_wbs_cyc),
.i_wb_stb(timer_wbs_stb),