new timer

cores/system/mcu/rtl/mcu_peripherals.v

@@ -44,7 +44,9 @@ module mcu_peripherals (
     wire [31:0] gpio_wbs_dat_r;
     wire gpio_wbs_ack;
 
+    wire [31:0] timer_wbs_adr = wbs_adr[1*32 +: 32];
     wire [31:0] timer_wbs_dat_w = wbs_dat_w[1*32 +: 32];
+    wire [3:0] timer_wbs_sel = wbs_sel[1*4 +: 4];
     wire timer_wbs_we = wbs_we[1];
     wire timer_wbs_cyc = wbs_cyc[1];
     wire timer_wbs_stb = wbs_stb[1];
@@ -108,12 +110,16 @@ module mcu_peripherals (
     assign wbs_dat_r[0*32 +: 32] = gpio_wbs_dat_r;
     assign wbs_ack[0] = gpio_wbs_ack;
 
-    wb_countdown_timer timer (
+    wb_countdown_timer #(
+        .address(TIMER_BASE_ADDR)
+    ) timer (
         .i_clk(i_clk),
         .i_rst(i_rst),
         .o_irq(o_timer_irq),
+        .i_wb_adr(timer_wbs_adr),
         .i_wb_dat(timer_wbs_dat_w),
         .o_wb_dat(timer_wbs_dat_r),
+        .i_wb_sel(timer_wbs_sel),
         .i_wb_we(timer_wbs_we),
         .i_wb_cyc(timer_wbs_cyc),
         .i_wb_stb(timer_wbs_stb),

cores/system/test/rtl/toplevel.v

@@ -1,7 +1,8 @@
 `timescale 1ns/1ps
 
 module toplevel #(
-    parameter sim = 0
+    parameter sim = 0,
+    parameter memfile = "sweep.hex"
 )(
     input wire aclk,
     input wire aresetn,
@@ -57,7 +58,7 @@ module toplevel #(
     wire test;
 
     mcu #(
-        .memfile("../sw/sweep/sweep.hex"),
+        .memfile(memfile),
         .sim(sim),
         .jtag(1)
     ) mcu (

cores/system/test/sw/sweep/sweep.c

@@ -6,7 +6,9 @@ static volatile uint32_t * const LEDS       = (volatile uint32_t *)(GPIO_BASE+4)
 static volatile uint32_t * const LEDGR      = (volatile uint32_t *)(GPIO_BASE+8);
 
 #define TIMER_BASE  0x40010000u
-static volatile uint32_t * const TIMER      = (volatile uint32_t *)(TIMER_BASE+0);
+static volatile uint32_t * const TIMER_CNT  = (volatile uint32_t *)(TIMER_BASE+0);
+static volatile uint32_t * const TIMER_LD   = (volatile uint32_t *)(TIMER_BASE+4);
+static volatile uint32_t * const TIMER_ACK  = (volatile uint32_t *)(TIMER_BASE+8);
 
 #define MSTATUS_MIE (1u << 3)
 #define MIE_MTIE    (1u << 7)
@@ -25,21 +27,21 @@ static inline void irq_init() {
 }
 
 void timer_isr(){
-    static int set = 0;
-    *TIMER = 1840000*8;
+    *TIMER_ACK = 1;
     *LEDGR = ~(*LEDGR);
 }
 
 void main(){
     irq_init();
 
-    *LEDGR = 3;
-    *TIMER = 1840000*2;
+    *LEDGR = 1;
+    *TIMER_LD = 2 * 15000000/1000;
 
     for(;;){
-        for(int i=1000; i<10000; i++){
+        for(int i=1000; i<10000; i+=10){
             *R_FREQ = i;
-            for(int j=0; j<80; j++) asm volatile("nop");
+            *LEDS = i>>4;
+            // for(int j=0; j<80; j++) asm volatile("nop");
         }
     }
 }

cores/system/test/tb/tb_toplevel.v

@@ -0,0 +1,37 @@
+`timescale 1ns/1ps
+
+module tb_toplevel;
+    reg        aclk;
+    reg        aresetn;
+    wire       led_green;
+    wire       led_red;
+    wire [5:0] r2r;
+    wire [7:0] LED;
+
+    toplevel #(
+        .sim(1)
+    ) dut (
+        .aclk(aclk),
+        .aresetn(aresetn),
+        .led_green(led_green),
+        .led_red(led_red),
+        .r2r(r2r),
+        .LED(LED)
+    );
+
+    initial aclk = 1'b0;
+    always #33.33 aclk = ~aclk;
+
+    initial begin
+        $dumpfile("toplevel.vcd");
+        $dumpvars(1, tb_toplevel);
+
+        aresetn = 1'b0;
+        #100;
+        aresetn = 1'b1;
+
+        #10_000_000;
+
+        $finish;
+    end
+endmodule

cores/system/test/test.core

@@ -13,10 +13,14 @@ filesets:
         files:
             - rtl/toplevel.v
         file_type: verilogSource
+    tb:
+        files:
+            - tb/tb_toplevel.v
+        file_type: verilogSource
 
     sw:
         files:
-            - sw/sweep/sweep.hex
+            - sw/sweep/sweep.hex : {copyto : sweep.hex}
         file_type: user
 
     mimas:
@@ -29,6 +33,13 @@ targets:
         filesets:
             - rtl
         toplevel: toplevel
+    sim:
+        default_tool: icarus
+        filesets:
+            - rtl
+            - sw
+            - tb
+        toplevel: tb_toplevel
 
     mimas:
         filesets: