Made timer synthesizable

cores/wb/wb_timer/formal/formal_wb_timer.v

@@ -17,9 +17,7 @@ module formal_wb_timer;
 
     assign i_wb_rst = 1'b0;
 
-    wb_countdown_timer #(
+    wb_countdown_timer dut (
-        .FORMAL(1)
-    ) dut (
         .i_clk(i_clk),
         .i_rst(i_rst),
         .o_irq(o_irq),

cores/wb/wb_timer/rtl/wb_timer.v

@@ -1,8 +1,7 @@
 `timescale 1ns/1ps
 
 module wb_countdown_timer #(
-    parameter address = 32'h00000000, // Base address of peripheral
+    parameter address = 32'h00000000 // Base address of peripheral
-    parameter FORMAL = 0
 )(
     input  wire         i_clk,
     input  wire         i_rst,
@@ -98,8 +97,8 @@ module wb_countdown_timer #(
         end
     end
 
+`ifdef FORMAL
     // Formal verification
-    if(FORMAL) begin
     reg f_past_valid = 1'b0;
     wire cnt_write = i_wb_cyc && i_wb_stb && i_wb_we && (i_wb_adr[3:0] == 4'h0);
     wire pld_write = i_wb_cyc && i_wb_stb && i_wb_we && (i_wb_adr[3:0] == 4'h4);
@@ -183,6 +182,6 @@ module wb_countdown_timer #(
         C6: cover(f_past_valid && $past(!i_rst) && $past(irq_fired) && !irq_fired && $past(ack_write));
 
     end
-    end;
+`endif
 
 endmodule

cores/wb/wb_timer/wb_timer.core

@@ -45,9 +45,14 @@ targets:
         toplevel: formal_wb_timer
         parameters:
             - address
+            - FORMAL=true
 
 parameters:
     address:
         datatype: int
         description: Base address of register set
         paramtype: vlogparam
+    FORMAL:
+        datatype: bool
+        description: Enable in-module formal-only logic
+        paramtype: vlogdefine