Added serv and made a blinky testbench for it

2026-02-21 19:24:18 +01:00
parent 3b04f3a6be
commit a261264fda
12 changed files with 284 additions and 2 deletions
--- a/rtl/core/sigmadelta_sampler.v
+++ b/rtl/core/sigmadelta_sampler.v
@@ -17,7 +17,7 @@ module sigmadelta_sampler(
    );

    reg registered_comp_out;
-    always @(posedge clk) registered_comp_out <= o;
+    always @(posedge clk) registered_comp_out <= comp_out;
    assign o = registered_comp_out;

 endmodule