joppe/fpga_modem
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Added serv and made a blinky testbench for it

Browse Source
This commit is contained in:
Joppe Blondel
2026-02-21 19:24:18 +01:00
parent 3b04f3a6be
commit a261264fda
12 changed files with 284 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
project.cfg
View File

@@ -12,6 +12,7 @@ pubkey = /home/joppe/.ssh/id_rsa.pub
[target.synth]
toolchain = ISE
ise_settings = /opt/packages/xilinx/14.7/ISE_DS/settings64.sh
# Toolchain settings
family = spartan6
device = xc6slx9
@@ -34,6 +35,38 @@ files_verilog = rtl/toplevel/top_generic.v
files_con = boards/mimas_v1/constraints.ucf
files_other = rtl/util/conv.vh
[target.serv]
toolchain = iverilog
runtime = all
toplevel = tb_serving
ivl_opts = -Irtl
files_verilog = external/serv/rtl/serv_aligner.v
external/serv/rtl/serv_alu.v
external/serv/rtl/serv_bufreg.v
external/serv/rtl/serv_bufreg2.v
external/serv/rtl/serv_compdec.v
external/serv/rtl/serv_csr.v
external/serv/rtl/serv_ctrl.v
external/serv/rtl/serv_debug.v
external/serv/rtl/serv_decode.v
external/serv/rtl/serv_immdec.v
external/serv/rtl/serv_mem_if.v
external/serv/rtl/serv_rf_if.v
external/serv/rtl/serv_rf_ram_if.v
external/serv/rtl/serv_rf_ram.v
external/serv/rtl/serv_rf_top.v
external/serv/rtl/serv_state.v
external/serv/rtl/serv_synth_wrapper.v
external/serv/rtl/serv_top.v
external/serv/servile/servile_arbiter.v
external/serv/servile/servile_mux.v
external/serv/servile/servile_rf_mem_if.v
external/serv/servile/servile.v
# external/serv/serving/serving_ram.v
sim/overrides/serving_ram.v
external/serv/serving/serving.v
sim/tb/tb_serving.v
[target.sim]
toolchain = iverilog
runtime = all