Working CPP way of writing data

project.cfg

@@ -21,7 +21,7 @@ device              = xc6slx9
 package             = tqg144
 speedgrade          = -2
 toplevel            = top_generic
-xst_opts            = -vlgincdir rtl/util
+xst_opts            = -vlgincdir rtl/util -keep_hierarchy yes
 files_verilog       = rtl/util/conv.vh
                       rtl/toplevel/top_generic.v
                       rtl/core/nco_q15.v
@@ -59,7 +59,8 @@ files_verilog       = rtl/util/conv.vh
                       rtl/serv/serving.v
                       rtl/wb/wb_gpio.v
                       rtl/wb/wb_gpio_banks.v
-                      rtl/core/soclet.v
+                      rtl/arch/spartan-6/jtag_if.v
+                      rtl/core/mcu.v
 files_con           = boards/mimas_v1/constraints.ucf
 files_other         = rtl/util/rc_alpha_q15.vh
                       rtl/util/clog2.vh