vibed jtagram with script as drop in replacement of serving_ram
This commit is contained in:
54
rtl/serv/serving_ram_dp.v
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54
rtl/serv/serving_ram_dp.v
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@@ -0,0 +1,54 @@
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`default_nettype none
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`include "../util/clog2.vh"
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module serving_ram_dp
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#(// Memory parameters
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parameter depth = 256,
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parameter aw = `CLOG2(depth),
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parameter memfile = "",
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parameter sim = 1'b0)
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(
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// CPU port (compatible with serving_ram)
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input wire i_clk,
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input wire [aw-1:0] i_waddr,
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input wire [7:0] i_wdata,
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input wire i_wen,
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input wire [aw-1:0] i_raddr,
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output reg [7:0] o_rdata,
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// Debug/programming port
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input wire i_dbg_clk,
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input wire [aw-1:0] i_dbg_addr,
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input wire [7:0] i_dbg_wdata,
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input wire i_dbg_wen,
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output wire [7:0] o_dbg_rdata
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);
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reg [7:0] mem [0:depth-1] /* verilator public */;
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always @(posedge i_clk) begin
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if (i_wen)
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mem[i_waddr] <= i_wdata;
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o_rdata <= mem[i_raddr];
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end
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always @(posedge i_dbg_clk) begin
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if (i_dbg_wen)
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mem[i_dbg_addr] <= i_dbg_wdata;
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end
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// Asynchronous debug read simplifies JTAG readback logic.
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assign o_dbg_rdata = mem[i_dbg_addr];
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integer i;
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initial begin
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if (sim == 1'b1) begin
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for (i = 0; i < depth; i = i + 1)
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mem[i] = 8'h00;
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end
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if (|memfile) begin
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$display("Preloading %m from %s", memfile);
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$readmemh(memfile, mem);
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end
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end
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endmodule
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65
rtl/serv/serving_ram_jtag.v
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65
rtl/serv/serving_ram_jtag.v
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@@ -0,0 +1,65 @@
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`default_nettype none
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`include "../util/clog2.vh"
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// Drop-in serving RAM variant with USER JTAG programming access.
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module serving_ram_jtag
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#(
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parameter depth = 256,
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parameter aw = `CLOG2(depth),
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parameter memfile = "",
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parameter sim = 1'b0,
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parameter USER_CHAIN = 1
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)
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(
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input wire i_clk,
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input wire [aw-1:0] i_waddr,
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input wire [7:0] i_wdata,
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input wire i_wen,
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input wire [aw-1:0] i_raddr,
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output wire [7:0] o_rdata
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);
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wire dbg_clk;
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wire [aw-1:0] dbg_addr;
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wire [7:0] dbg_wdata;
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wire dbg_wen;
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wire [7:0] dbg_rdata;
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serving_ram_dp
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#(
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.depth(depth),
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.aw(aw),
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.memfile(memfile),
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.sim(sim)
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)
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i_serving_ram_dp
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(
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.i_clk(i_clk),
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.i_waddr(i_waddr),
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.i_wdata(i_wdata),
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.i_wen(i_wen),
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.i_raddr(i_raddr),
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.o_rdata(o_rdata),
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.i_dbg_clk(dbg_clk),
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.i_dbg_addr(dbg_addr),
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.i_dbg_wdata(dbg_wdata),
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.i_dbg_wen(dbg_wen),
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.o_dbg_rdata(dbg_rdata)
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);
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serving_ram_jtag_bridge
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#(
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.depth(depth),
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.aw(aw),
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.USER_CHAIN(USER_CHAIN)
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)
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i_serving_ram_jtag_bridge
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(
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.o_ram_clk(dbg_clk),
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.o_ram_addr(dbg_addr),
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.o_ram_wdata(dbg_wdata),
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.o_ram_wen(dbg_wen),
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.i_ram_rdata(dbg_rdata)
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);
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endmodule
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107
rtl/serv/serving_ram_jtag_bridge.v
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107
rtl/serv/serving_ram_jtag_bridge.v
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`default_nettype none
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`include "../util/clog2.vh"
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// Simple USER JTAG data-register protocol (LSB-first):
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// bit[0] : write_enable (1=write, 0=read/select)
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// bit[32:1] : 32-bit address
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// bit[40:33] : write data
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//
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// On UPDATE:
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// - write command: writes byte to RAM
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// - read command : updates current read address for next CAPTURE/SHIFT readback
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// - RAM uses the lower aw address bits from the 32-bit protocol address
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//
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// On CAPTURE, readback register loads:
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// bit[0] : valid (always 1)
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// bit[8:1] : read data at current read address
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// remaining bits : zero
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module serving_ram_jtag_bridge
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#(
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parameter depth = 256,
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parameter aw = `CLOG2(depth),
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parameter USER_CHAIN = 1
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)
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(
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output wire o_ram_clk,
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output wire [aw-1:0] o_ram_addr,
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output wire [7:0] o_ram_wdata,
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output wire o_ram_wen,
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input wire [7:0] i_ram_rdata
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);
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localparam integer JTAG_AW = 32;
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localparam integer FRAME_W = 1 + JTAG_AW + 8;
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localparam integer PAD_W = FRAME_W - 9;
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wire tap_drck;
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wire tap_shift;
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wire tap_update;
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wire tap_reset;
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wire tap_sel;
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wire tap_tdi;
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wire tap_tdo;
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reg [FRAME_W-1:0] shift_in;
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reg [FRAME_W-1:0] shift_out;
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reg [aw-1:0] read_addr;
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reg shift_active_d;
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wire cmd_write;
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wire [JTAG_AW-1:0] cmd_addr;
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wire [aw-1:0] cmd_addr_ram;
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wire [7:0] cmd_wdata;
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assign cmd_write = shift_in[0];
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assign cmd_addr = shift_in[JTAG_AW:1];
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assign cmd_wdata = shift_in[JTAG_AW+8:JTAG_AW+1];
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assign cmd_addr_ram = cmd_addr[aw-1:0];
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// Update command shift register and shift response out on DRCK.
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// Readback data is loaded on the first shift pulse of a DR scan.
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always @(posedge tap_drck or posedge tap_reset) begin
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if (tap_reset) begin
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shift_in <= {FRAME_W{1'b0}};
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shift_out <= {FRAME_W{1'b0}};
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shift_active_d <= 1'b0;
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end else if (tap_sel && tap_shift) begin
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if (!shift_active_d)
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shift_out <= {{PAD_W{1'b0}}, i_ram_rdata, 1'b1};
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else
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shift_out <= {1'b0, shift_out[FRAME_W-1:1]};
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shift_in <= {tap_tdi, shift_in[FRAME_W-1:1]};
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shift_active_d <= 1'b1;
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end else begin
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shift_active_d <= 1'b0;
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end
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end
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// Read command selects the address for the next capture.
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always @(posedge tap_update or posedge tap_reset) begin
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if (tap_reset)
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read_addr <= {aw{1'b0}};
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else if (tap_sel && !cmd_write)
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read_addr <= cmd_addr_ram;
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end
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assign o_ram_clk = tap_update;
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assign o_ram_wen = tap_update & tap_sel & cmd_write;
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assign o_ram_wdata = cmd_wdata;
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assign o_ram_addr = tap_update ? cmd_addr_ram : read_addr;
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assign tap_tdo = shift_out[0];
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jtag_tap_spartan6
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#(.USER_CHAIN(USER_CHAIN))
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i_jtag_tap
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(
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.o_drck(tap_drck),
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.o_capture(),
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.o_shift(tap_shift),
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.o_update(tap_update),
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.o_reset(tap_reset),
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.o_sel(tap_sel),
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.o_tdi(tap_tdi),
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.i_tdo(tap_tdo)
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);
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endmodule
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