Using remotesyn and added NCO
This commit is contained in:
Jojojoppe
176
rtl/core/nco_q15.v
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176
rtl/core/nco_q15.v
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@@ -0,0 +1,176 @@
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`timescale 1ns/1ps
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// ------------------------------------------------------------
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// nco_q15.v
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// Tiny DDS/NCO @ FS_HZ sample rate with Q1.15 sine/cos outputs
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// - Phase accumulator width: PHASE_BITS (default 32)
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// - Quarter-wave LUT: 2^QTR_ADDR_BITS entries (default 64)
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// - Clock domain: CLK_HZ (default 120 MHz), creates 1-cycle strobe at FS_HZ
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// - Frequency control: write 'ftw' (32-bit tuning word)
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// FTW = round(f_out * 2^PHASE_BITS / FS_HZ)
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// ------------------------------------------------------------
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module nco_q15 #
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(
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// -------- Synth parameters --------
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parameter integer PHASE_BITS = 32, // accumulator width
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parameter integer QTR_ADDR_BITS = 6, // 64-entry quarter-wave LUT
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parameter integer CLK_HZ = 120_000_000, // input clock (Hz)
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parameter integer FS_HZ = 40_000 // output sample rate (Hz)
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)
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(
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input wire clk, // CLK_HZ domain
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input wire rst_n, // async active-low reset
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// Frequency control
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input wire [31:0] ftw_in, // Frequency Tuning Word (FTW)
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input wire ftw_we, // write-enable strobe (1 clk pulse)
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// Outputs (valid on clk_en rising pulse, i.e., at FS_HZ)
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output reg signed [15:0] sin_q15, // signed Q1.15 sine
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output reg signed [15:0] cos_q15, // signed Q1.15 cosine
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output reg clk_en // 1-cycle strobe @ FS_HZ
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);
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`include "core/nco_q15_funcs.vh"
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// ==========================================================
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// Sample-rate enable: divide CLK_HZ down to FS_HZ
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// - DIV must be an integer (CLK_HZ / FS_HZ).
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// - clk_en goes high for exactly 1 clk cycle every DIV cycles.
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// ==========================================================
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localparam integer DIV = CLK_HZ / FS_HZ;
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// Optional safety for misconfiguration (ignored by synthesis tools):
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initial if (CLK_HZ % FS_HZ != 0)
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$display("WARNING nco_q15: CLK_HZ (%0d) not divisible by FS_HZ (%0d).", CLK_HZ, FS_HZ);
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// Counter width: enough bits to count to DIV-1 (use a generous fixed width to keep 2001-compatible)
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// If you prefer, replace 16 with $clog2(DIV) on a tool that supports it well.
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reg [15:0] tick_cnt;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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tick_cnt <= 16'd0;
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clk_en <= 1'b0;
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end else begin
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if (tick_cnt == DIV-1) begin
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tick_cnt <= 16'd0;
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clk_en <= 1'b1; // 1-cycle pulse
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end else begin
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tick_cnt <= tick_cnt + 16'd1;
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clk_en <= 1'b0;
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end
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end
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end
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// ==========================================================
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// Frequency control register
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// - You present ftw_in and pulse ftw_we (1 clk) to update.
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// ==========================================================
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reg [31:0] ftw;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) ftw <= ftw_from_hz(1000, PHASE_BITS, FS_HZ); // Start at 1khz
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else if (ftw_we) ftw <= ftw_in;
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end
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// ==========================================================
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// Phase accumulators
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// - phase_sin advances by FTW once per sample (on clk_en).
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// - cosine is generated by a +90° phase lead (π/2), i.e., add 2^(PHASE_BITS-2).
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// Here we realize it by deriving phase_cos from phase_sin each sample.
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// ==========================================================
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reg [PHASE_BITS-1:0] phase_sin, phase_cos;
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wire [PHASE_BITS-1:0] phase_cos_plus90 = phase_sin + ({{(PHASE_BITS-2){1'b0}}, 2'b01} << (PHASE_BITS-2)); // +90°
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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phase_sin <= {PHASE_BITS{1'b0}};
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phase_cos <= {PHASE_BITS{1'b0}};
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end else if (clk_en) begin
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phase_sin <= phase_sin + ftw;
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// Keep cosine aligned to the same sample using a +90° offset from updated phase_sin
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phase_cos <= phase_cos_plus90 + ftw;
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end
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end
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// ==========================================================
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// Phase -> quadrant/index
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// - q_*: top 2 bits select quadrant (0..3).
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// - idx_*_raw: next QTR_ADDR_BITS select a point in 0..π/2.
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// - For odd quadrants, mirror the LUT index.
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// ==========================================================
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wire [1:0] q_sin = phase_sin[PHASE_BITS-1 -: 2];
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wire [1:0] q_cos = phase_cos[PHASE_BITS-1 -: 2];
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wire [QTR_ADDR_BITS-1:0] idx_sin_raw = phase_sin[PHASE_BITS-3 -: QTR_ADDR_BITS];
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wire [QTR_ADDR_BITS-1:0] idx_cos_raw = phase_cos[PHASE_BITS-3 -: QTR_ADDR_BITS];
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wire [QTR_ADDR_BITS-1:0] idx_sin = (q_sin[0]) ? ({QTR_ADDR_BITS{1'b1}} - idx_sin_raw) : idx_sin_raw;
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wire [QTR_ADDR_BITS-1:0] idx_cos = (q_cos[0]) ? ({QTR_ADDR_BITS{1'b1}} - idx_cos_raw) : idx_cos_raw;
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// ==========================================================
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// Quarter-wave 8-bit LUT (0..255). 64 entries map 0..π/2.
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// ==========================================================
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wire [7:0] lut_sin_mag, lut_cos_mag;
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sine_qtr_lut64 u_lut_s (.addr(idx_sin), .dout(lut_sin_mag));
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sine_qtr_lut64 u_lut_c (.addr(idx_cos), .dout(lut_cos_mag));
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// ==========================================================
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// Sign & scale to Q1.15
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// - Scale: <<7 so 255 becomes 32640 (slightly below 32767).
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// - Apply sign by quadrant: quadrants 2 & 3 are negative.
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// ==========================================================
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wire signed [15:0] sin_mag_q15 = {1'b0, lut_sin_mag, 7'd0};
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wire signed [15:0] cos_mag_q15 = {1'b0, lut_cos_mag, 7'd0};
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wire sin_neg = (q_sin >= 2); // quadrants 2,3
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wire cos_neg = (q_cos >= 2);
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wire signed [15:0] sin_q15_next = sin_neg ? -sin_mag_q15 : sin_mag_q15;
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wire signed [15:0] cos_q15_next = cos_neg ? -cos_mag_q15 : cos_mag_q15;
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// ==========================================================
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// Output registers (update on clk_en)
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// ==========================================================
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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sin_q15 <= 16'sd0;
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cos_q15 <= 16'sd0;
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end else if (clk_en) begin
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sin_q15 <= sin_q15_next;
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cos_q15 <= cos_q15_next;
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end
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end
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endmodule
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// ------------------------------------------------------------
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// 64-entry quarter-wave sine ROM (8-bit), indices 0..63 map 0..π/2.
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// Plain Verilog case ROM. You can regenerate these with a script
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// or replace with a vendor-specific ROM for BRAM inference.
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// ------------------------------------------------------------
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module sine_qtr_lut64(
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input wire [5:0] addr,
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output reg [7:0] dout
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);
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always @* begin
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case (addr)
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6'd0: dout = 8'd0; 6'd1: dout = 8'd6; 6'd2: dout = 8'd13; 6'd3: dout = 8'd19;
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6'd4: dout = 8'd25; 6'd5: dout = 8'd31; 6'd6: dout = 8'd37; 6'd7: dout = 8'd44;
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6'd8: dout = 8'd50; 6'd9: dout = 8'd56; 6'd10: dout = 8'd62; 6'd11: dout = 8'd68;
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6'd12: dout = 8'd74; 6'd13: dout = 8'd80; 6'd14: dout = 8'd86; 6'd15: dout = 8'd92;
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6'd16: dout = 8'd98; 6'd17: dout = 8'd103; 6'd18: dout = 8'd109; 6'd19: dout = 8'd115;
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6'd20: dout = 8'd120; 6'd21: dout = 8'd126; 6'd22: dout = 8'd131; 6'd23: dout = 8'd136;
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6'd24: dout = 8'd142; 6'd25: dout = 8'd147; 6'd26: dout = 8'd152; 6'd27: dout = 8'd157;
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6'd28: dout = 8'd162; 6'd29: dout = 8'd167; 6'd30: dout = 8'd171; 6'd31: dout = 8'd176;
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6'd32: dout = 8'd180; 6'd33: dout = 8'd185; 6'd34: dout = 8'd189; 6'd35: dout = 8'd193;
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6'd36: dout = 8'd197; 6'd37: dout = 8'd201; 6'd38: dout = 8'd205; 6'd39: dout = 8'd208;
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6'd40: dout = 8'd212; 6'd41: dout = 8'd215; 6'd42: dout = 8'd219; 6'd43: dout = 8'd222;
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6'd44: dout = 8'd225; 6'd45: dout = 8'd228; 6'd46: dout = 8'd231; 6'd47: dout = 8'd233;
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6'd48: dout = 8'd236; 6'd49: dout = 8'd238; 6'd50: dout = 8'd240; 6'd51: dout = 8'd242;
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6'd52: dout = 8'd244; 6'd53: dout = 8'd246; 6'd54: dout = 8'd247; 6'd55: dout = 8'd249;
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6'd56: dout = 8'd250; 6'd57: dout = 8'd251; 6'd58: dout = 8'd252; 6'd59: dout = 8'd253;
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6'd60: dout = 8'd254; 6'd61: dout = 8'd254; 6'd62: dout = 8'd255; 6'd63: dout = 8'd255;
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default: dout=8'd0;
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endcase
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end
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endmodule
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24
rtl/core/nco_q15_funcs.vh
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24
rtl/core/nco_q15_funcs.vh
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@@ -0,0 +1,24 @@
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// ==========================================================
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// Helper: FTW function (compile-time or runtime call)
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// FTW = round( f_hz * 2^PHASE_BITS / FS_HZ )
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// Notes:
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// - Accepts integer Hz.
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// - Uses 64-bit math to avoid overflow for typical params.
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// - Can be called from a testbench or combinational logic that
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// prepares 'ftw_in' before asserting 'ftw_we'.
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// Example:
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// initial begin
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// #1;
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// $display("FTW 1kHz = 0x%08x", ftw_from_hz(1000));
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// end
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// ==========================================================
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function [31:0] ftw_from_hz;
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input integer f_hz;
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input integer phase_bits;
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input integer fs_hz;
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reg [63:0] numer;
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begin
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numer = ((64'd1 << phase_bits) * f_hz) + (fs_hz/2);
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ftw_from_hz = numer / fs_hz;
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end
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endfunction
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45
rtl/toplevel/top_generic.v
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45
rtl/toplevel/top_generic.v
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`timescale 1ns/1ps
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module top_generic(
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input wire aclk,
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input wire aresetn,
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output wire led_green,
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output wire led_red,
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output wire[5:0] r2r
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);
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`include "core/nco_q15_funcs.vh"
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assign led_green = 1'b0;
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assign led_red = 1'b0;
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wire [15:0] sin_q15;
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wire clk_en;
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nco_q15 #(
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.CLK_HZ(100_000_000),
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.PHASE_BITS(16)
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) nco (
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.clk (aclk),
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.rst_n (aresetn),
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.ftw_in (32'h0),
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.ftw_we (1'b0),
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.sin_q15(sin_q15),
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.cos_q15(),
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.clk_en (clk_en)
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);
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// sin_q15: signed Q15 in [-32768, +32767]
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wire signed [15:0] s = sin_q15;
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// Bias to 0..65535 and round before downscaling by 1024 (>>10)
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wire [16:0] biased = s + 17'sd32768; // 0..65535
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wire [5:0] dac_code_next = biased[15:10]; // 0..63 (MSB=bit5)
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// Register it at the sample rate (clk_en)
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reg [5:0] dac_code;
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always @(posedge aclk or negedge aresetn) begin
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if (!aresetn) dac_code <= 6'd0;
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else if (clk_en) dac_code <= dac_code_next;
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end
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assign r2r = dac_code;
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endmodule
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