24 lines
788 B
Systemverilog
24 lines
788 B
Systemverilog
// ==========================================================
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// Helper: FTW function (compile-time or runtime call)
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// FTW = round( f_hz * 2^PHASE_BITS / FS_HZ )
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// Notes:
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// - Accepts integer Hz.
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// - Uses 64-bit math to avoid overflow for typical params.
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// - Can be called from a testbench or combinational logic that
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// prepares 'ftw_in' before asserting 'ftw_we'.
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// Example:
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// initial begin
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// #1;
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// $display("FTW 1kHz = 0x%08x", ftw_from_hz(1000));
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// end
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// ==========================================================
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function [31:0] ftw_from_hz;
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input integer f_hz;
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input integer phase_bits;
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input integer fs_hz;
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reg [63:0] numer;
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begin
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numer = ((64'd1 << phase_bits) * f_hz) + (fs_hz/2);
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ftw_from_hz = numer / fs_hz;
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end
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endfunction |