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TImer working with tests

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TODO: think of other way of shifting in data. Bit errors make uploading difficult
This commit is contained in:
Joppe Blondel
2026-02-25 22:01:28 +01:00
parent 3a3c951409
commit 838204653a
7 changed files with 142 additions and 16 deletions
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11
rtl/wb/jtag_wb_bridge.v
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@@ -107,7 +107,7 @@ module jtag_wb_bridge #(
reg [31:0] wb_dat_r;
reg [3:0] wb_sel_r;
reg wb_we_r;
reg cmd_reset_pulse_r;
reg cmd_reset_level_r;
reg [31:0] resp_addr_r;
reg [7:0] resp_data_r;
@@ -133,7 +133,7 @@ module jtag_wb_bridge #(
assign o_wb_we = wb_we_r;
assign o_wb_cyc = wb_busy;
assign o_wb_stb = wb_busy;
assign o_cmd_reset = cmd_reset_pulse_r;
assign o_cmd_reset = cmd_reset_level_r;
always @(posedge i_clk) begin
if (i_rst) begin
@@ -148,7 +148,7 @@ module jtag_wb_bridge #(
wb_dat_r <= 32'b0;
wb_sel_r <= 4'b0000;
wb_we_r <= 1'b0;
cmd_reset_pulse_r <= 1'b0;
cmd_reset_level_r <= 1'b0;
resp_addr_r <= 32'b0;
resp_data_r <= 8'b0;
end else begin
@@ -157,12 +157,11 @@ module jtag_wb_bridge #(
s_req_sync_3 <= s_req_sync_2;
s_cmd_sync_1 <= j_cmd_hold;
s_cmd_sync_2 <= s_cmd_sync_1;
cmd_reset_pulse_r <= 1'b0;
if (req_pulse && !wb_busy) begin
wb_busy <= 1'b1;
wb_we_r <= cmd_we;
wb_adr_r <= cmd_addr;
cmd_reset_level_r <= cmd_reset;
case (req_lane)
2'b00: begin wb_sel_r <= 4'b0001; wb_dat_r <= {24'b0, cmd_wdata}; end
@@ -170,8 +169,6 @@ module jtag_wb_bridge #(
2'b10: begin wb_sel_r <= 4'b0100; wb_dat_r <= {8'b0, cmd_wdata, 16'b0}; end
default: begin wb_sel_r <= 4'b1000; wb_dat_r <= {cmd_wdata, 24'b0}; end
endcase
cmd_reset_pulse_r <= cmd_reset;
end
if (wb_busy && i_wb_ack) begin