TImer working with tests

TODO: think of other way of shifting in data. Bit errors make uploading difficult

rtl/toplevel/top_generic.v

@@ -23,6 +23,26 @@ module top_generic #(
         .clk_out_15(clk_15)
     );
 
+    // Reset conditioning for button input:
+    // - asynchronous assert when button is pressed (aresetn=0)
+    // - synchronous, debounced deassert in clk_15 domain
+    localparam [17:0] RESET_RELEASE_CYCLES = sim ? 18'd16 : 18'd150000; // ~10 ms @ 15 MHz on hardware
+    reg [17:0] rst_cnt = 18'd0;
+    reg        sys_reset_r = 1'b1;
+    always @(posedge clk_15 or negedge aresetn) begin
+        if (!aresetn) begin
+            rst_cnt <= 18'd0;
+            sys_reset_r <= 1'b1;
+        end else if (sys_reset_r) begin
+            if (rst_cnt == RESET_RELEASE_CYCLES - 1'b1)
+                sys_reset_r <= 1'b0;
+            else
+                rst_cnt <= rst_cnt + 1'b1;
+        end
+    end
+    wire sys_reset = sys_reset_r;
+    wire sys_resetn = !sys_reset_r;
+
     wire [31:0] GPIO_A;
     wire [31:0] GPIO_B;
     wire [31:0] GPIO_C;
@@ -35,7 +55,7 @@ module top_generic #(
         .sim(sim)
     ) mcu (
         .i_clk(clk_15),
-        .i_rst(!aresetn),
+        .i_rst(sys_reset),
         .i_GPI_A(GPIO_A),
         .i_GPI_B(GPIO_B),
         .i_GPI_C(GPIO_C),
@@ -55,7 +75,7 @@ module top_generic #(
         .FS_HZ(80_000)
     ) nco (
         .clk    (clk_15),
-        .rst_n  (aresetn),
+        .rst_n  (sys_resetn),
         .freq_hz(GPIO_A),
         .sin_q15(sin_q15),
         .cos_q15(),