TImer working with tests

TODO: think of other way of shifting in data. Bit errors make uploading difficult
2026-02-25 22:01:28 +01:00
parent 3a3c951409
commit 838204653a
7 changed files with 142 additions and 16 deletions
--- a/rtl/core/mcu.v
+++ b/rtl/core/mcu.v
@@ -88,7 +88,7 @@ module mcu #(
    ) servile (
        .i_clk(i_clk),
        .i_rst(rst),
-        .i_timer_irq(1'b0), //timer_irq),
+        .i_timer_irq(timer_irq),

        //Memory interface
        .o_wb_mem_adr(wb_mem_adr),