TImer working with tests

TODO: think of other way of shifting in data. Bit errors make uploading difficult

rtl/core/mcu.v

@@ -88,7 +88,7 @@ module mcu #(
     ) servile (
         .i_clk(i_clk),
         .i_rst(rst),
-        .i_timer_irq(1'b0), //timer_irq),
+        .i_timer_irq(timer_irq),
 
         //Memory interface
         .o_wb_mem_adr(wb_mem_adr),

rtl/toplevel/top_generic.v

@@ -23,6 +23,26 @@ module top_generic #(
         .clk_out_15(clk_15)
     );
 
+    // Reset conditioning for button input:
+    // - asynchronous assert when button is pressed (aresetn=0)
+    // - synchronous, debounced deassert in clk_15 domain
+    localparam [17:0] RESET_RELEASE_CYCLES = sim ? 18'd16 : 18'd150000; // ~10 ms @ 15 MHz on hardware
+    reg [17:0] rst_cnt = 18'd0;
+    reg        sys_reset_r = 1'b1;
+    always @(posedge clk_15 or negedge aresetn) begin
+        if (!aresetn) begin
+            rst_cnt <= 18'd0;
+            sys_reset_r <= 1'b1;
+        end else if (sys_reset_r) begin
+            if (rst_cnt == RESET_RELEASE_CYCLES - 1'b1)
+                sys_reset_r <= 1'b0;
+            else
+                rst_cnt <= rst_cnt + 1'b1;
+        end
+    end
+    wire sys_reset = sys_reset_r;
+    wire sys_resetn = !sys_reset_r;
+
     wire [31:0] GPIO_A;
     wire [31:0] GPIO_B;
     wire [31:0] GPIO_C;
@@ -35,7 +55,7 @@ module top_generic #(
         .sim(sim)
     ) mcu (
         .i_clk(clk_15),
-        .i_rst(!aresetn),
+        .i_rst(sys_reset),
         .i_GPI_A(GPIO_A),
         .i_GPI_B(GPIO_B),
         .i_GPI_C(GPIO_C),
@@ -55,7 +75,7 @@ module top_generic #(
         .FS_HZ(80_000)
     ) nco (
         .clk    (clk_15),
-        .rst_n  (aresetn),
+        .rst_n  (sys_resetn),
         .freq_hz(GPIO_A),
         .sin_q15(sin_q15),
         .cos_q15(),

rtl/wb/jtag_wb_bridge.v

@@ -107,7 +107,7 @@ module jtag_wb_bridge #(
     reg [31:0] wb_dat_r;
     reg [3:0] wb_sel_r;
     reg wb_we_r;
-    reg cmd_reset_pulse_r;
+    reg cmd_reset_level_r;
     reg [31:0] resp_addr_r;
     reg [7:0] resp_data_r;
 
@@ -133,7 +133,7 @@ module jtag_wb_bridge #(
     assign o_wb_we = wb_we_r;
     assign o_wb_cyc = wb_busy;
     assign o_wb_stb = wb_busy;
-    assign o_cmd_reset = cmd_reset_pulse_r;
+    assign o_cmd_reset = cmd_reset_level_r;
 
     always @(posedge i_clk) begin
         if (i_rst) begin
@@ -148,7 +148,7 @@ module jtag_wb_bridge #(
             wb_dat_r <= 32'b0;
             wb_sel_r <= 4'b0000;
             wb_we_r <= 1'b0;
-            cmd_reset_pulse_r <= 1'b0;
+            cmd_reset_level_r <= 1'b0;
             resp_addr_r <= 32'b0;
             resp_data_r <= 8'b0;
         end else begin
@@ -157,12 +157,11 @@ module jtag_wb_bridge #(
             s_req_sync_3 <= s_req_sync_2;
             s_cmd_sync_1 <= j_cmd_hold;
             s_cmd_sync_2 <= s_cmd_sync_1;
-            cmd_reset_pulse_r <= 1'b0;
-
             if (req_pulse && !wb_busy) begin
                 wb_busy <= 1'b1;
                 wb_we_r <= cmd_we;
                 wb_adr_r <= cmd_addr;
+                cmd_reset_level_r <= cmd_reset;
 
                 case (req_lane)
                     2'b00: begin wb_sel_r <= 4'b0001; wb_dat_r <= {24'b0, cmd_wdata}; end
@@ -170,8 +169,6 @@ module jtag_wb_bridge #(
                     2'b10: begin wb_sel_r <= 4'b0100; wb_dat_r <= {8'b0, cmd_wdata, 16'b0}; end
                     default: begin wb_sel_r <= 4'b1000; wb_dat_r <= {cmd_wdata, 24'b0}; end
                 endcase
-
-                cmd_reset_pulse_r <= cmd_reset;
             end
 
             if (wb_busy && i_wb_ack) begin