Added decimator

SIM/sampling_tb.v

@@ -1,11 +1,13 @@
 `timescale 1ns/1ps
 
 module sampling_tb;
-    reg clk;
+    reg clk_15;
+    reg clk_120;
     reg reset_n;
 
     sampling m_sampling(
-        .clk(clk),
+        .clk_15(clk_15),
+        .clk_120(clk_120),
         .reset_n(reset_n)
     );
 
@@ -13,15 +15,16 @@ module sampling_tb;
         $dumpfile("sampling_tb.vcd");
         $dumpvars (0, sampling_tb);
 
-        clk <= 1'b0;
+        clk_15 <= 1'b0;
+        clk_120 <= 1'b0;
         reset_n <= 1'b0;
         #50 reset_n <= 1'b1;
 
-        #1000000
+        #2000000
         $finish;
     end
 
-    //15 MHz clock
-    always #33.33 clk = ~clk;
+    always #(500/15) clk_15 = ~clk_15;
+    always #(500/120) clk_120 = ~clk_120;
 
 endmodule

SIM/sigmadelta_sampler.v

@@ -8,7 +8,7 @@ module sigmadelta_sampler(
 );
     // ===== Tunable parameters =====
     // Sine source (A input / P)
-    parameter real    F_HZ       = 2.0e3;   // input sine frequency (1 kHz)
+    parameter real    F_HZ       = 1.5e3;   // input sine frequency (1 kHz)
     parameter real    AMP        = 1.5;     // sine amplitude (V)
     parameter real    VCM        = 1.65;    // common-mode (V), centered in 0..3.3V