Working SERV cpu

rtl/toplevel/top_serv.v

@@ -10,6 +10,15 @@ module top_generic(
     output wire[5:0] r2r
 );
 
+    // Clocking
+    wire clk_100;
+    wire clk_15;
+    assign clk_100 = aclk;
+    clk_gen clocking(
+        .clk_in(clk_100),
+        .clk_out_15(clk_15)
+    );
+
     wire [31:0] wb_adr;
     wire [31:0] wb_dat;
     wire [31:0] wb_rdt;
@@ -31,7 +40,7 @@ module top_generic(
         .RESET_STRATEGY("MINI"),
         .WITH_CSR(1)
     ) serv (
-        .i_clk(aclk),
+        .i_clk(clk_15),
         .i_rst(!aresetn),
         .i_timer_irq(1'b0),
         .i_wb_rdt(wb_rdt),
@@ -44,9 +53,9 @@ module top_generic(
     );
 
     wb_gpio #(
-      .address(32'h80000000)
+      .address(32'h40000000)
     ) gpio (
-        .i_wb_clk(aclk),
+        .i_wb_clk(clk_15),
         .i_wb_rst(!aresetn),
         .i_wb_dat(wb_dat),
         .i_wb_adr(wb_adr),