Working SERV cpu

rtl/toplevel/top_generic.v

@@ -26,7 +26,7 @@ module top_generic(
     localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz
     reg [16:0] div_counter = 0;               // enough bits for 100k (2^17=131072)
     reg [31:0] freq;
-    always @(posedge aclk) begin
+    always @(posedge clk_15) begin
         if (!aresetn) begin
             div_counter <= 0;
             count <= 0;
@@ -48,10 +48,10 @@ module top_generic(
     wire [15:0] sin_q15;
     wire clk_en;
     nco_q15 #(
-        .CLK_HZ(100_000_000),
+        .CLK_HZ(15_000_000),
         .FS_HZ(40_000)
     ) nco (
-        .clk    (aclk),
+        .clk    (clk_15),
         .rst_n  (aresetn),
         .freq_hz(freq),
         .sin_q15(sin_q15),
@@ -60,7 +60,7 @@ module top_generic(
     );
 
     reg [5:0] dac_code;
-    always @(posedge aclk) begin
+    always @(posedge clk_15) begin
         dac_code <= q15_to_uq16(sin_q15) >> 10;
     end
     assign r2r = dac_code;