Working SERV cpu

rtl/serv/serving_ram.v

@@ -18,28 +18,37 @@
  */
 
 `default_nettype none
+`include "../util/clog2.vh"
 module serving_ram
   #(//Memory parameters
-    parameter depth = 256,
-    parameter aw    = $clog2(depth),
-    parameter memfile = "")
+	parameter depth = 256,
+	parameter aw    = `CLOG2(depth),
+	parameter memfile = "",
+	parameter sim = 1'b0)
    (input wire		i_clk,
-    input wire [aw-1:0]	i_waddr,
-    input wire [7:0]	i_wdata,
-    input wire		i_wen,
-    input wire [aw-1:0]	i_raddr,
-    output reg [7:0]	o_rdata);
+	input wire [aw-1:0]	i_waddr,
+	input wire [7:0]	i_wdata,
+	input wire		i_wen,
+	input wire [aw-1:0]	i_raddr,
+	output reg [7:0]	o_rdata);
 
-   reg [7:0]		mem [0:depth-1] /* verilator public */;
+   	reg [7:0]		mem [0:depth-1] /* verilator public */;
 
-   always @(posedge i_clk) begin
-      if (i_wen) mem[i_waddr]   <= i_wdata;
-      o_rdata <= mem[i_raddr];
+	always @(posedge i_clk) begin
+		if (i_wen) mem[i_waddr]   <= i_wdata;
+		o_rdata <= mem[i_raddr];
+	end
+
+	integer i;
+   	initial begin
+		if(sim==1'b1) begin
+			for (i = 0; i < depth; i = i + 1)
+				mem[i] = 8'h00;
+
+		end
+		if(|memfile) begin
+			$display("Preloading %m from %s", memfile);
+			$readmemh(memfile, mem);
+		end
    end
-
-   initial
-     if(|memfile) begin
-	$display("Preloading %m from %s", memfile);
-	$readmemh(memfile, mem);
-     end
 endmodule