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Working SERV cpu

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This commit is contained in:
Joppe Blondel
2026-02-22 18:48:17 +01:00
parent ac6aea90b6
commit 5e951f9b61
24 changed files with 534 additions and 157 deletions
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10
rtl/serv/serving.v
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@@ -18,6 +18,7 @@
*/
`default_nettype none
`include "../util/clog2.vh"
module serving
(
input wire i_clk,
@@ -56,16 +57,17 @@ module serving
wire [rf_width-1:0] rf_rdata;
wire rf_ren;
wire [$clog2(memsize)-1:0] sram_waddr;
wire [`CLOG2(memsize)-1:0] sram_waddr;
wire [rf_width-1:0] sram_wdata;
wire sram_wen;
wire [$clog2(memsize)-1:0] sram_raddr;
wire [`CLOG2(memsize)-1:0] sram_raddr;
wire [rf_width-1:0] sram_rdata;
wire sram_ren;
serving_ram
#(.memfile (memfile),
.depth (memsize))
.depth (memsize),
.sim (sim))
ram
(// Wishbone interface
.i_clk (i_clk),
@@ -98,7 +100,7 @@ module serving
.i_sram_rdata (sram_rdata),
.o_sram_ren (sram_ren),
.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
.i_wb_adr (wb_mem_adr[`CLOG2(memsize)-1:2]),
.i_wb_stb (wb_mem_stb),
.i_wb_we (wb_mem_we) ,
.i_wb_sel (wb_mem_sel),