Working SERV cpu

rtl/serv/serv_rf_ram.v

@@ -4,15 +4,16 @@
  * SPDX-FileCopyrightText: 2019 Olof Kindgren <olof@award-winning.me>
  * SPDX-License-Identifier: ISC
  */
+`include "../util/clog2.vh"
 module serv_rf_ram
   #(parameter width=0,
     parameter csr_regs=4,
     parameter depth=32*(32+csr_regs)/width)
    (input wire i_clk,
-    input wire [$clog2(depth)-1:0] i_waddr,
+    input wire [`CLOG2(depth)-1:0] i_waddr,
     input wire [width-1:0] 	   i_wdata,
     input wire 			   i_wen,
-    input wire [$clog2(depth)-1:0] i_raddr,
+    input wire [`CLOG2(depth)-1:0] i_raddr,
     input wire			   i_ren,
     output wire [width-1:0] 	   o_rdata);
 
@@ -28,7 +29,7 @@ module serv_rf_ram
    /* Reads from reg x0 needs to return 0
     Check that the part of the read address corresponding to the register
     is zero and gate the output
-    width LSB of reg index $clog2(width)
+    width LSB of reg index `CLOG2(width)
     2     4                1
     4     3                2
     8     2                3
@@ -38,7 +39,7 @@ module serv_rf_ram
    reg regzero;
 
    always @(posedge i_clk)
-     regzero <= !(|i_raddr[$clog2(depth)-1:5-$clog2(width)]);
+     regzero <= !(|i_raddr[`CLOG2(depth)-1:5-`CLOG2(width)]);
 
    assign o_rdata = rdata & ~{width{regzero}};