Working SERV cpu

rtl/arch/spartan-6/clk_gen.v

@@ -67,9 +67,9 @@
 (* CORE_GENERATION_INFO = "clk_gen,clk_wiz_v3_6,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
 module clk_gen
  (// Clock in ports
-  input         clk_in,
+  input  wire   clk_in,
   // Clock out ports
-  output        clk_out_15
+  output wire   clk_out_15
  );
 
   // Input buffering
@@ -78,6 +78,7 @@ module clk_gen
   //  (.O (clkin1),
     // .I (clk_in));
 
+  wire clkin1;
   assign clkin1 = clk_in;
 
   // Clocking primitive
@@ -145,4 +146,3 @@ module clk_gen
 
 
 endmodule
-