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Working SERV cpu

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This commit is contained in:
Joppe Blondel
2026-02-22 18:48:17 +01:00
parent ac6aea90b6
commit 5e951f9b61
24 changed files with 534 additions and 157 deletions
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6
rtl/arch/spartan-6/clk_gen.v
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@@ -67,9 +67,9 @@
(* CORE_GENERATION_INFO = "clk_gen,clk_wiz_v3_6,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clk_gen
(// Clock in ports
input clk_in,
input wire clk_in,
// Clock out ports
output clk_out_15
output wire clk_out_15
);
// Input buffering
@@ -78,6 +78,7 @@ module clk_gen
// (.O (clkin1),
// .I (clk_in));
wire clkin1;
assign clkin1 = clk_in;
// Clocking primitive
@@ -145,4 +146,3 @@ module clk_gen
endmodule

9
rtl/serv/serv_rf_ram.v
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@@ -4,15 +4,16 @@
* SPDX-FileCopyrightText: 2019 Olof Kindgren <olof@award-winning.me>
* SPDX-License-Identifier: ISC
*/
`include "../util/clog2.vh"
module serv_rf_ram
#(parameter width=0,
parameter csr_regs=4,
parameter depth=32*(32+csr_regs)/width)
(input wire i_clk,
input wire [$clog2(depth)-1:0] i_waddr,
input wire [`CLOG2(depth)-1:0] i_waddr,
input wire [width-1:0] i_wdata,
input wire i_wen,
input wire [$clog2(depth)-1:0] i_raddr,
input wire [`CLOG2(depth)-1:0] i_raddr,
input wire i_ren,
output wire [width-1:0] o_rdata);
@@ -28,7 +29,7 @@ module serv_rf_ram
/* Reads from reg x0 needs to return 0
Check that the part of the read address corresponding to the register
is zero and gate the output
width LSB of reg index $clog2(width)
width LSB of reg index `CLOG2(width)
2 4 1
4 3 2
8 2 3
@@ -38,7 +39,7 @@ module serv_rf_ram
reg regzero;
always @(posedge i_clk)
regzero <= !(|i_raddr[$clog2(depth)-1:5-$clog2(width)]);
regzero <= !(|i_raddr[`CLOG2(depth)-1:5-`CLOG2(width)]);
assign o_rdata = rdata & ~{width{regzero}};

10
rtl/serv/serv_rf_ram_if.v
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@@ -5,7 +5,7 @@
* SPDX-License-Identifier: ISC
*/
`default_nettype none
// `include "../util/clog2.vh"
`include "../util/clog2.vh"
module serv_rf_ram_if
#(//Data width. Adjust to preferred width of SRAM data interface
parameter width=8,
@@ -22,8 +22,8 @@ module serv_rf_ram_if
//Internal parameters calculated from above values. Do not change
parameter B=W-1,
parameter raw=clog2(32+csr_regs), //Register address width
parameter l2w=clog2(width), //log2 of width
parameter raw=`CLOG2(32+csr_regs), //Register address width
parameter l2w=`CLOG2(width), //log2 of width
parameter aw=5+raw-l2w) //Address width
(
//SERV side
@@ -51,8 +51,8 @@ module serv_rf_ram_if
input wire [width-1:0] i_rdata);
localparam ratio = width/W;
localparam CMSB = 4-clog2(W); //Counter MSB
localparam l2r = clog2(ratio);
localparam CMSB = 4-`CLOG2(W); //Counter MSB
localparam l2r = `CLOG2(ratio);
reg rgnt;
assign o_ready = rgnt | i_wreq;

3
rtl/serv/serv_rf_top.v
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@@ -5,6 +5,7 @@
* SPDX-License-Identifier: ISC
*/
`default_nettype none
`include "../util/clog2.vh"
module serv_rf_top
#(parameter RESET_PC = 32'd0,
@@ -37,7 +38,7 @@ module serv_rf_top
parameter WITH_CSR = 1,
parameter W = 1,
parameter RF_WIDTH = W * 2,
parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
parameter RF_L2D = `CLOG2((32+(WITH_CSR*4))*32/RF_WIDTH))
(
input wire clk,
input wire i_rst,

3
rtl/serv/serv_synth_wrapper.v
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@@ -5,6 +5,7 @@
* SPDX-License-Identifier: ISC
*/
`default_nettype none
`include "../util/clog2.vh"
module serv_synth_wrapper
#(
@@ -22,7 +23,7 @@ module serv_synth_wrapper
parameter RESET_STRATEGY = "MINI",
parameter WITH_CSR = 1,
parameter RF_WIDTH = 2,
parameter RF_L2D = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
parameter RF_L2D = `CLOG2((32+(WITH_CSR*4))*32/RF_WIDTH))
(
input wire clk,
input wire i_rst,

11
rtl/serv/servile.v
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@@ -6,6 +6,7 @@
*/
`default_nettype none
`include "../util/clog2.vh"
module servile
#(
parameter width = 1,
@@ -20,7 +21,7 @@ module servile
//Internally calculated. Do not touch
parameter B = width-1,
parameter regs = 32+with_csr*4,
parameter rf_l2d = $clog2(regs*32/rf_width))
parameter rf_l2d = `CLOG2(regs*32/rf_width))
(
input wire i_clk,
input wire i_rst,
@@ -77,14 +78,14 @@ module servile
wire rf_wreq;
wire rf_rreq;
wire [$clog2(regs)-1:0] wreg0;
wire [$clog2(regs)-1:0] wreg1;
wire [`CLOG2(regs)-1:0] wreg0;
wire [`CLOG2(regs)-1:0] wreg1;
wire wen0;
wire wen1;
wire [B:0] wdata0;
wire [B:0] wdata1;
wire [$clog2(regs)-1:0] rreg0;
wire [$clog2(regs)-1:0] rreg1;
wire [`CLOG2(regs)-1:0] rreg0;
wire [`CLOG2(regs)-1:0] rreg1;
wire rf_ready;
wire [B:0] rdata0;
wire [B:0] rdata1;

5
rtl/serv/servile_rf_mem_if.v
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@@ -6,14 +6,15 @@
*/
`default_nettype none
`include "../util/clog2.vh"
module servile_rf_mem_if
#(//Memory parameters
parameter depth = 256,
//RF parameters
parameter rf_regs = 32,
//Internally calculated. Do not touch
parameter rf_depth = $clog2(rf_regs*4),
parameter aw = $clog2(depth))
parameter rf_depth = `CLOG2(rf_regs*4),
parameter aw = `CLOG2(depth))
(
input wire i_clk,
input wire i_rst,

10
rtl/serv/serving.v
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@@ -18,6 +18,7 @@
*/
`default_nettype none
`include "../util/clog2.vh"
module serving
(
input wire i_clk,
@@ -56,16 +57,17 @@ module serving
wire [rf_width-1:0] rf_rdata;
wire rf_ren;
wire [$clog2(memsize)-1:0] sram_waddr;
wire [`CLOG2(memsize)-1:0] sram_waddr;
wire [rf_width-1:0] sram_wdata;
wire sram_wen;
wire [$clog2(memsize)-1:0] sram_raddr;
wire [`CLOG2(memsize)-1:0] sram_raddr;
wire [rf_width-1:0] sram_rdata;
wire sram_ren;
serving_ram
#(.memfile (memfile),
.depth (memsize))
.depth (memsize),
.sim (sim))
ram
(// Wishbone interface
.i_clk (i_clk),
@@ -98,7 +100,7 @@ module serving
.i_sram_rdata (sram_rdata),
.o_sram_ren (sram_ren),
.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
.i_wb_adr (wb_mem_adr[`CLOG2(memsize)-1:2]),
.i_wb_stb (wb_mem_stb),
.i_wb_we (wb_mem_we) ,
.i_wb_sel (wb_mem_sel),

45
rtl/serv/serving_ram.v
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@@ -18,28 +18,37 @@
*/
`default_nettype none
`include "../util/clog2.vh"
module serving_ram
#(//Memory parameters
parameter depth = 256,
parameter aw = $clog2(depth),
parameter memfile = "")
parameter depth = 256,
parameter aw = `CLOG2(depth),
parameter memfile = "",
parameter sim = 1'b0)
(input wire i_clk,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output reg [7:0] o_rdata);
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output reg [7:0] o_rdata);
reg [7:0] mem [0:depth-1] /* verilator public */;
reg [7:0] mem [0:depth-1] /* verilator public */;
always @(posedge i_clk) begin
if (i_wen) mem[i_waddr] <= i_wdata;
o_rdata <= mem[i_raddr];
always @(posedge i_clk) begin
if (i_wen) mem[i_waddr] <= i_wdata;
o_rdata <= mem[i_raddr];
end
integer i;
initial begin
if(sim==1'b1) begin
for (i = 0; i < depth; i = i + 1)
mem[i] = 8'h00;
end
if(|memfile) begin
$display("Preloading %m from %s", memfile);
$readmemh(memfile, mem);
end
end
initial
if(|memfile) begin
$display("Preloading %m from %s", memfile);
$readmemh(memfile, mem);
end
endmodule

8
rtl/toplevel/top_generic.v
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@@ -26,7 +26,7 @@ module top_generic(
localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz
reg [16:0] div_counter = 0; // enough bits for 100k (2^17=131072)
reg [31:0] freq;
always @(posedge aclk) begin
always @(posedge clk_15) begin
if (!aresetn) begin
div_counter <= 0;
count <= 0;
@@ -48,10 +48,10 @@ module top_generic(
wire [15:0] sin_q15;
wire clk_en;
nco_q15 #(
.CLK_HZ(100_000_000),
.CLK_HZ(15_000_000),
.FS_HZ(40_000)
) nco (
.clk (aclk),
.clk (clk_15),
.rst_n (aresetn),
.freq_hz(freq),
.sin_q15(sin_q15),
@@ -60,7 +60,7 @@ module top_generic(
);
reg [5:0] dac_code;
always @(posedge aclk) begin
always @(posedge clk_15) begin
dac_code <= q15_to_uq16(sin_q15) >> 10;
end
assign r2r = dac_code;

15
rtl/toplevel/top_serv.v
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@@ -10,6 +10,15 @@ module top_generic(
output wire[5:0] r2r
);
// Clocking
wire clk_100;
wire clk_15;
assign clk_100 = aclk;
clk_gen clocking(
.clk_in(clk_100),
.clk_out_15(clk_15)
);
wire [31:0] wb_adr;
wire [31:0] wb_dat;
wire [31:0] wb_rdt;
@@ -31,7 +40,7 @@ module top_generic(
.RESET_STRATEGY("MINI"),
.WITH_CSR(1)
) serv (
.i_clk(aclk),
.i_clk(clk_15),
.i_rst(!aresetn),
.i_timer_irq(1'b0),
.i_wb_rdt(wb_rdt),
@@ -44,9 +53,9 @@ module top_generic(
);
wb_gpio #(
.address(32'h80000000)
.address(32'h40000000)
) gpio (
.i_wb_clk(aclk),
.i_wb_clk(clk_15),
.i_wb_rst(!aresetn),
.i_wb_dat(wb_dat),
.i_wb_adr(wb_adr),

49
rtl/util/clog2.vh
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@@ -1,10 +1,39 @@
function integer clog2;
input integer value;
integer i;
begin
value = value - 1;
for (i = 0; value > 0; i = i + 1)
value = value >> 1;
clog2 = (i < 1) ? 1 : i;
end
endfunction
`ifndef CLOG2_VH
`define CLOG2_VH
// Verilog-2001 compatible ceil(log2(x)) macro (matches $clog2 semantics).
`define CLOG2(x) \
(((x) <= 1) ? 0 : \
((x) <= 2) ? 1 : \
((x) <= 4) ? 2 : \
((x) <= 8) ? 3 : \
((x) <= 16) ? 4 : \
((x) <= 32) ? 5 : \
((x) <= 64) ? 6 : \
((x) <= 128) ? 7 : \
((x) <= 256) ? 8 : \
((x) <= 512) ? 9 : \
((x) <= 1024) ? 10 : \
((x) <= 2048) ? 11 : \
((x) <= 4096) ? 12 : \
((x) <= 8192) ? 13 : \
((x) <= 16384) ? 14 : \
((x) <= 32768) ? 15 : \
((x) <= 65536) ? 16 : \
((x) <= 131072) ? 17 : \
((x) <= 262144) ? 18 : \
((x) <= 524288) ? 19 : \
((x) <= 1048576) ? 20 : \
((x) <= 2097152) ? 21 : \
((x) <= 4194304) ? 22 : \
((x) <= 8388608) ? 23 : \
((x) <= 16777216) ? 24 : \
((x) <= 33554432) ? 25 : \
((x) <= 67108864) ? 26 : \
((x) <= 134217728) ? 27 : \
((x) <= 268435456) ? 28 : \
((x) <= 536870912) ? 29 : \
((x) <= 1073741824) ? 30 : \
((x) <= 2147483648) ? 31 : 32)
`endif