Working SERV cpu

project.cfg

@@ -13,14 +13,14 @@ pubkey              = /home/joppe/.ssh/id_rsa.pub
 [target.synth]
 toolchain           = ISE
 ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
-# Toolchain settings
 family              = spartan6
 device              = xc6slx9
 package             = tqg144
 speedgrade          = -2
 toplevel            = top_generic
 xst_opts            = -vlgincdir rtl/util
-files_verilog       = rtl/toplevel/top_generic.v
+files_verilog       = rtl/util/conv.vh
+                      rtl/toplevel/top_generic.v
                       rtl/core/nco_q15.v
                       rtl/core/sigmadelta_sampler.v
                       rtl/core/sigmadelta_rcmodel_q15.v
@@ -31,17 +31,17 @@ files_verilog       = rtl/toplevel/top_generic.v
                       rtl/arch/spartan-6/lvds_comparator.v
                       rtl/arch/spartan-6/clk_gen.v
 files_con           = boards/mimas_v1/constraints.ucf
-files_other         = rtl/util/conv.vh
-                      rtl/util/rc_alpha_q15.vh
+files_other         = rtl/util/rc_alpha_q15.vh
 
 [target.ip]
 toolchain           = ISE_IP
+ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
 family              = spartan6
 device              = xc6slx9
 package             = tqg144
 speedgrade          = -2
-files_xco           = boards/mimas_v1/ip/clk_gen.xco
-
+files_def           = boards/mimas_v1/ip/mem_8kx8b.xco
+                      #boards/mimas_v1/ip/clk_gen.xco
 
 [target.serv]
 toolchain           = ISE
@@ -54,8 +54,8 @@ toplevel            = top_generic
 xst_opts            = -vlgincdir rtl
 files_con           = boards/mimas_v1/constraints.ucf
 files_other         = sw/blinky/blinky.hex
-files_verilog       = rtl/util/clog2.vh
-                      rtl/serv/serv_aligner.v
+                      rtl/util/clog2.vh
+files_verilog       = rtl/serv/serv_aligner.v
                       rtl/serv/serv_alu.v
                       rtl/serv/serv_bufreg.v
                       rtl/serv/serv_bufreg2.v
@@ -78,8 +78,8 @@ files_verilog       = rtl/util/clog2.vh
                       rtl/serv/servile_rf_mem_if.v
                       rtl/serv/servile.v
                       rtl/serv/serving_ram.v
-                      # sim/overrides/serving_ram.v
                       rtl/serv/serving.v
+                      rtl/arch/spartan-6/clk_gen.v
                       rtl/wb/wb_gpio.v
                       rtl/toplevel/top_serv.v
 
@@ -101,4 +101,40 @@ files_verilog       = sim/tb/tb_nco_q15.v
                       sim/overrides/sigmadelta_sampler.v
                       sim/overrides/clk_gen.v
 files_other         = rtl/util/conv.vh
-                      rtl/util/rc_alpha_q15.vh
+                      rtl/util/rc_alpha_q15.vh
+
+[target.servsim]
+toolchain           = iverilog
+runtime             = all
+toplevel            = tb_serving
+ivl_opts            = -Irtl/util
+files_other         = sw/blinky/blinky.hex
+                      rtl/util/clog2.vh
+files_verilog       = rtl/serv/serv_aligner.v
+                      rtl/serv/serv_alu.v
+                      rtl/serv/serv_bufreg.v
+                      rtl/serv/serv_bufreg2.v
+                      rtl/serv/serv_compdec.v
+                      rtl/serv/serv_csr.v
+                      rtl/serv/serv_ctrl.v
+                      rtl/serv/serv_debug.v
+                      rtl/serv/serv_decode.v
+                      rtl/serv/serv_immdec.v
+                      rtl/serv/serv_mem_if.v
+                      rtl/serv/serv_rf_if.v
+                      rtl/serv/serv_rf_ram_if.v
+                      rtl/serv/serv_rf_ram.v
+                      rtl/serv/serv_rf_top.v
+                      rtl/serv/serv_state.v
+                      rtl/serv/serv_synth_wrapper.v
+                      rtl/serv/serv_top.v
+                      rtl/serv/servile_arbiter.v
+                      rtl/serv/servile_mux.v
+                      rtl/serv/servile_rf_mem_if.v
+                      rtl/serv/servile.v
+                      rtl/serv/serving_ram.v
+                      rtl/serv/serving.v
+                      rtl/arch/spartan-6/clk_gen.v
+                      rtl/wb/wb_gpio.v
+                      rtl/toplevel/top_serv.v
+                      sim/tb/tb_serving.v