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Combined all sigmadelta things to one input block

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Joppe Blondel
2025-10-19 20:03:51 +02:00
parent 165faefa59
commit 49b8a77480
5 changed files with 137 additions and 66 deletions
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35
sim/tb/tb_sigmadelta.v
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@@ -20,32 +20,17 @@ module tb_sigmadelta();
wire sd_a;
wire sd_b;
wire sd_o;
// 3K3R 220PC 15MHZT
sigmadelta_sampler sd_sampler(
.clk(clk),
.a(sd_a), .b(sd_b),
.o(sd_o)
);
wire signed [15:0] sample_q15;
sigmadelta_rcmodel_q15 rc_model(
.clk(clk), .resetn(resetn),
.sd_sample(sd_o),
.sample_q15(sample_q15)
);
wire signed [15:0] y_q15;
lpf_iir_q15_k #(10) lpf(
.clk(clk), .rst_n(resetn),
.x_q15(sample_q15),
.y_q15(y_q15)
);
wire signed [15:0] decimated_q15;
decimate_by_r_q15 #(400, 10) decimate(
.clk(clk), .rst_n(resetn),
.in_valid(1'b1), .in_q15(y_q15),
.out_valid(), .out_q15(decimated_q15)
wire decimated_valid;
sigmadelta_input #(
.R_OHM(3300),
.C_PF(220)
) dut(
.clk_15(clk), .resetn(resetn),
.adc_a(sd_a), .adc_b(sd_b), .adc_o(sd_o),
.signal_q15(decimated_q15),
.signal_valid(decimated_valid)
);
endmodule