Combined all sigmadelta things to one input block

project.cfg

@@ -22,6 +22,7 @@ files_verilog       = rtl/toplevel/top_generic.v
                       rtl/core/nco_q15.v
                       rtl/core/sigmadelta_sampler.v
                       rtl/core/sigmadelta_rcmodel_q15.v
+                      rtl/core/sigmadelta_input_q15.v
                       rtl/core/mul_const.v
                       rtl/core/lpf_iir_q15_k.v
                       rtl/core/decimate_by_r_q15.v
@@ -51,6 +52,7 @@ files_verilog       = sim/tb/tb_nco_q15.v
                       rtl/core/nco_q15.v
                       rtl/core/lvds_comparator.v
                       rtl/core/sigmadelta_rcmodel_q15.v
+                      rtl/core/sigmadelta_input_q15.v
                       rtl/core/mul_const.v
                       rtl/core/lpf_iir_q15_k.v
                       rtl/core/decimate_by_r_q15.v