initial commit

SIM/globals.v

@@ -0,0 +1,9 @@
+`timescale 1ns/1ps
+module glbl;
+    reg gsri = 0;
+    initial begin
+    #10 gsri = 1;  // release reset after 100ns
+    end
+
+    GSR GSR (.GSRI(gsri));
+endmodule

SIM/toplevel_tb.v

@@ -0,0 +1,42 @@
+`timescale 1ns/1ps
+
+module toplevel_tb;
+    reg clk;
+    reg reset_n;
+    reg button;
+    wire led;
+
+    toplevel m_toplevel(
+        .clk(clk),
+        .reset_n(reset_n),
+        .button(button),
+        .led(led)
+    );
+
+    initial begin
+        $dumpfile("toplevel_tb.vcd");
+        $dumpvars (0, toplevel_tb);
+
+        clk <= 1'b0;
+        reset_n <= 1'b0;
+        button <= 1'b0;
+
+        #50 reset_n <= 1'b1;
+
+        #70 button <= 1'b1;
+
+        #185 button <= 1'b0;
+
+        #200
+        $finish;
+    end
+
+    always #37 clk = ~clk;
+
+`ifdef TIMING_SIM
+    initial begin
+        $sdf_annotate("impl/pnr/modem.sdf", m_toplevel, , , "MAXIMUM");
+    end
+`endif
+
+endmodule