initial commit

IP/ge_pllvr/gw_pllvr.ipc

@@ -0,0 +1,25 @@
+[General]
+file=gw_pllvr
+ipc_version=4
+module=gw_pllvr
+target_device=gw1nsr4c-009
+type=clock_pllvr
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=27
+CLKOUTD=false
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=120
+CLKOUT_TOLERANCE=0
+DYNAMIC=true
+LANG=0
+LOCK_EN=false
+MODE_GENERAL=true
+PLL_PWD=false
+PLL_REGULATOR=false
+RESET_PLL=true

IP/ge_pllvr/gw_pllvr.mod

@@ -0,0 +1,34 @@
+-series GW1NSR
+-device GW1NSR-4C
+-device_version 
+-package QFN48P
+-part_number GW1NSR-LV4CQN48PC7/I6
+
+
+-mod_name gw_pllvr
+-file_name gw_pllvr
+-path /data/joppe/projects/modem/IP/ge_pllvr/
+-type PLL
+-pllvr true
+-file_type vlg
+-dev_type GW1NSR-4C
+-dyn_idiv_sel false
+-idiv_sel 9
+-dyn_fbdiv_sel false
+-fbdiv_sel 40
+-dyn_odiv_sel false
+-odiv_sel 8
+-dyn_da_en true
+-rst_sig true
+-rst_sig_p false
+-pll_reg false
+-fclkin 27
+-clkfb_sel 0
+-en_lock false
+-clkout_bypass false
+-clkout_ft_dir 1
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd false
+-clkoutd_bypass false
+-en_clkoutd3 false

IP/ge_pllvr/gw_pllvr.v

@@ -0,0 +1,67 @@
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.12
+//Part Number: GW1NSR-LV4CQN48PC7/I6
+//Device: GW1NSR-4C
+//Created Time: Wed Oct  1 13:08:32 2025
+
+module gw_pllvr (clkout, reset, clkin);
+
+output clkout;
+input reset;
+input clkin;
+
+wire lock_o;
+wire clkoutp_o;
+wire clkoutd_o;
+wire clkoutd3_o;
+wire gw_vcc;
+wire gw_gnd;
+
+assign gw_vcc = 1'b1;
+assign gw_gnd = 1'b0;
+
+PLLVR pllvr_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock_o),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd_o),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(reset),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .VREN(gw_vcc)
+);
+
+defparam pllvr_inst.FCLKIN = "27";
+defparam pllvr_inst.DYN_IDIV_SEL = "false";
+defparam pllvr_inst.IDIV_SEL = 8;
+defparam pllvr_inst.DYN_FBDIV_SEL = "false";
+defparam pllvr_inst.FBDIV_SEL = 39;
+defparam pllvr_inst.DYN_ODIV_SEL = "false";
+defparam pllvr_inst.ODIV_SEL = 8;
+defparam pllvr_inst.PSDA_SEL = "0000";
+defparam pllvr_inst.DYN_DA_EN = "true";
+defparam pllvr_inst.DUTYDA_SEL = "1000";
+defparam pllvr_inst.CLKOUT_FT_DIR = 1'b1;
+defparam pllvr_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam pllvr_inst.CLKOUT_DLY_STEP = 0;
+defparam pllvr_inst.CLKOUTP_DLY_STEP = 0;
+defparam pllvr_inst.CLKFB_SEL = "internal";
+defparam pllvr_inst.CLKOUT_BYPASS = "false";
+defparam pllvr_inst.CLKOUTP_BYPASS = "false";
+defparam pllvr_inst.CLKOUTD_BYPASS = "false";
+defparam pllvr_inst.DYN_SDIV_SEL = 2;
+defparam pllvr_inst.CLKOUTD_SRC = "CLKOUT";
+defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam pllvr_inst.DEVICE = "GW1NSR-4C";
+
+endmodule //gw_pllvr

IP/ge_pllvr/gw_pllvr_tmp.v

@@ -0,0 +1,18 @@
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.12
+//Part Number: GW1NSR-LV4CQN48PC7/I6
+//Device: GW1NSR-4C
+//Created Time: Wed Oct  1 13:08:32 2025
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    gw_pllvr your_instance_name(
+        .clkout(clkout), //output clkout
+        .reset(reset), //input reset
+        .clkin(clkin) //input clkin
+    );
+
+//--------Copy end-------------------