joppe/fpga_modem
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Jojojoppe
2025-10-01 16:40:05 +02:00
commit 42e9bd0a0a
18 changed files with 147564 additions and 0 deletions
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16
CON/io.cst Normal file
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//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.12
//Part Number: GW1NSR-LV4CQN48PC7/I6
//Device: GW1NSR-4C
//Created Time: Wed 10 01 13:41:57 2025
IO_LOC "led" 10;
IO_PORT "led" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "button" 14;
IO_PORT "button" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "reset_n" 15;
IO_PORT "reset_n" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "clk" 45;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

6
CON/timing.sdc Normal file
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//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.12
//Created Time: 2025-10-01 13:43:45
create_clock -name CLK_IN -period 37.037 -waveform {0 18.518} [get_ports {clk}]