Added lvds and sampler

rtl/core/lvds_comparator.v

@@ -0,0 +1,13 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// LVDS comparator
+// Simple pass-though model
+// =============================================================================
+module lvds_comparator(
+    input wire a,
+    input wire b,
+    output wire o
+);
+    assign o = a;
+endmodule