Added lvds and sampler

rtl/arch/gw1/lvds_comparator.v

@@ -0,0 +1,17 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// LVDS comparator
+// Instantiating a GW1 TLVDS_IBUF
+// =============================================================================
+module lvds_comparator(
+    input wire a,
+    input wire b,
+    output wire o
+);
+    TLVDS_IBUF lvds_buf (
+        .O(o),
+        .I(a),
+        .IB(b)
+    );
+endmodule

rtl/arch/spartan-6/lvds_comparator.v

@@ -0,0 +1,20 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// LVDS comparator
+// Instantiating a spartan-6 IBUFDS
+// =============================================================================
+module lvds_comparator(
+    input wire a,
+    input wire b,
+    output wire o
+);
+    IBUFDS #(
+        .DIFF_TERM("FALSE"),
+        .IOSTANDARD("LVDS33")
+    ) lvds_buf (
+        .O(o),
+        .I(a),
+        .IB(b)
+    );
+endmodule

rtl/core/lvds_comparator.v

@@ -0,0 +1,13 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// LVDS comparator
+// Simple pass-though model
+// =============================================================================
+module lvds_comparator(
+    input wire a,
+    input wire b,
+    output wire o
+);
+    assign o = a;
+endmodule

rtl/core/sigmadelta_sampler.v

@@ -0,0 +1,23 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// Sigma-Delta sampler
+// Samples A>B at clk
+// =============================================================================
+module sigmadelta_sampler(
+    input wire clk,
+    input wire a,
+    input wire b,
+    output wire o
+);
+
+    wire comp_out;
+    lvds_comparator comp (
+        .a(a), .b(b), .o(comp_out)
+    );
+
+    reg registered_comp_out;
+    always @(posedge clk) registered_comp_out <= o;
+    assign o = registered_comp_out;
+
+endmodule