Added lvds and sampler

2025-10-08 18:01:03 +02:00
parent 324bb108e3
commit 3b04f3a6be
6 changed files with 188 additions and 0 deletions
--- a/project.cfg
+++ b/project.cfg
@@ -29,6 +29,8 @@ xst_opts            = -vlgincdir rtl
 #files_vhdl          = 
 files_verilog       = rtl/toplevel/top_generic.v
                      rtl/core/nco_q15.v
+                      rtl/core/sigmadelta_sampler.v
+                      rtl/arch/spartan-6/lvds_comparator.v
 files_con           = boards/mimas_v1/constraints.ucf
 files_other         = rtl/util/conv.vh

@@ -42,4 +44,6 @@ ivl_opts            = -Irtl
 #files_sysverilog    = 
 files_verilog       = sim/tb/tb_nco_q15.v
                      rtl/core/nco_q15.v
+                      rtl/core/lvds_comparator.v
+                      sim/overrides/sigmadelta_sampler.v
 files_other         = rtl/util/conv.vh