New wishbone-jtag bridge
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70
rtl/core/cdc_req_resp.v
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70
rtl/core/cdc_req_resp.v
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`timescale 1 ns/1 ps
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// =============================================================================
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// cdc_req_resp
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// Bidirectional channel made from two cdc_strobe_data mailboxes.
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// =============================================================================
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module cdc_req_resp #(
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parameter integer REQ_W = 32,
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parameter integer RESP_W = 32,
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parameter integer STABLE_SAMPLES = 2
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)(
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// Side A (e.g., JTAG/TCK)
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input wire a_clk,
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input wire a_rst,
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input wire a_req_pulse,
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input wire [REQ_W-1:0] a_req_data,
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output wire a_req_busy,
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output wire a_req_accepted,
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output wire a_resp_pulse,
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output wire [RESP_W-1:0] a_resp_data,
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// Side B (e.g., system/i_clk)
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input wire b_clk,
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input wire b_rst,
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output wire b_req_pulse,
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output wire [REQ_W-1:0] b_req_data,
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input wire b_resp_pulse,
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input wire [RESP_W-1:0] b_resp_data,
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output wire b_resp_busy,
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output wire b_resp_accepted
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);
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cdc_strobe_data #(
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.WIDTH(REQ_W),
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.STABLE_SAMPLES(STABLE_SAMPLES)
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) u_req (
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.s_clk(a_clk),
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.s_rst(a_rst),
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.s_pulse(a_req_pulse),
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.s_data(a_req_data),
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.s_busy(a_req_busy),
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.s_accepted(a_req_accepted),
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.d_clk(b_clk),
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.d_rst(b_rst),
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.d_pulse(b_req_pulse),
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.d_data(b_req_data)
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);
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cdc_strobe_data #(
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.WIDTH(RESP_W),
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.STABLE_SAMPLES(STABLE_SAMPLES)
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) u_resp (
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.s_clk(b_clk),
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.s_rst(b_rst),
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.s_pulse(b_resp_pulse),
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.s_data(b_resp_data),
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.s_busy(b_resp_busy),
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.s_accepted(b_resp_accepted),
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.d_clk(a_clk),
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.d_rst(a_rst),
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.d_pulse(a_resp_pulse),
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.d_data(a_resp_data)
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);
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endmodule
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