Added timer, still wip

This commit is contained in:
2026-02-25 20:54:12 +01:00
parent f2f9644830
commit 3a3c951409
12 changed files with 768 additions and 203 deletions

45
sim/tb/tb_top_generic.v Normal file
View File

@@ -0,0 +1,45 @@
`timescale 1ns/1ps
module tb_top_generic();
reg aclk;
reg aresetn;
wire led_green;
wire led_red;
wire [5:0] r2r;
wire [7:0] LED;
// 100 MHz board input clock
initial aclk = 1'b0;
always #5 aclk = ~aclk;
// Hold reset low, then release
initial begin
aresetn = 1'b0;
#200;
aresetn = 1'b1;
end
top_generic #(
.sim(1)
) dut (
.aclk(aclk),
.aresetn(aresetn),
.led_green(led_green),
.led_red(led_red),
.r2r(r2r),
.LED(LED)
);
// Ensure firmware path resolves from repository root when simulating.
defparam dut.mcu.memfile = "sw/sweep/sweep.hex";
initial begin
$dumpfile("out.vcd");
$dumpvars(0, tb_top_generic);
// Let firmware run for a while.
#5_000_000;
$finish;
end
endmodule