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Added planahead script and fixed conversion

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Jojojoppe
2025-10-06 16:49:28 +02:00
parent 06ef70e1ee
commit 324bb108e3
5 changed files with 24 additions and 15 deletions
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4
project.cfg
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@@ -30,7 +30,7 @@ xst_opts = -vlgincdir rtl
files_verilog = rtl/toplevel/top_generic.v files_verilog = rtl/toplevel/top_generic.v
rtl/core/nco_q15.v rtl/core/nco_q15.v
files_con = boards/mimas_v1/constraints.ucf files_con = boards/mimas_v1/constraints.ucf
files_other = files_other = rtl/util/conv.vh
[target.sim] [target.sim]
toolchain = iverilog toolchain = iverilog
@@ -42,4 +42,4 @@ ivl_opts = -Irtl
#files_sysverilog = #files_sysverilog =
files_verilog = sim/tb/tb_nco_q15.v files_verilog = sim/tb/tb_nco_q15.v
rtl/core/nco_q15.v rtl/core/nco_q15.v
files_other = files_other = rtl/util/conv.vh

11
rtl/toplevel/top_generic.v
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@@ -9,7 +9,7 @@ module top_generic(
output wire[5:0] r2r output wire[5:0] r2r
); );
`include "util/conv.vh"
assign led_green = 1'b0; assign led_green = 1'b0;
assign led_red = 1'b0; assign led_red = 1'b0;
@@ -51,16 +51,9 @@ module top_generic(
.clk_en (clk_en) .clk_en (clk_en)
); );
// sin_q15: signed Q15 in [-32768, +32767]
wire signed [15:0] s = sin_q15;
// Bias to 0..65535 and round before downscaling by 1024 (>>10)
wire [16:0] biased = s + 17'sd32768; // 0..65535
wire [5:0] dac_code_next = biased[15:10]; // 0..63 (MSB=bit5)
// Register it at the sample rate (clk_en)
reg [5:0] dac_code; reg [5:0] dac_code;
always @(posedge aclk) begin always @(posedge aclk) begin
if (!aresetn) dac_code <= 6'd0; dac_code <= q15_to_uq16(sin_q15) >> 10;
else dac_code <= dac_code_next;
end end
assign r2r = dac_code; assign r2r = dac_code;
endmodule endmodule

11
rtl/util/conv.vh Normal file
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@@ -0,0 +1,11 @@
// =============================================================================
// Convert Q1.15 to a biased UQ0.16 signal
// =============================================================================
function [15:0] q15_to_uq16;
input [15:0] q15;
reg [16:0] biased;
begin
biased = q15 + 17'sd32768;
q15_to_uq16 = biased[15:0];
end
endfunction

4
scripts/planahead.sh Executable file
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@@ -0,0 +1,4 @@
#!/bin/bash
cd build
. /opt/packages/xilinx/ISE/14.7/ISE_DS/settings64.sh
planAhead -mode gui -source ../scripts/planahead.tcl

9
scripts/planahead.tcl
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@@ -1,6 +1,7 @@
create_project project_1 /tmp/project_1 -part xc6slx9tqg144-2 create_project project_1 tmpplanahead -part xc6slx9tqg144-2 -force
set_property design_mode GateLvl [current_fileset] set_property design_mode GateLvl [current_fileset]
add_files -norecurse /data/joppe/projects/modem/out/synth/synth.ngc add_files -norecurse ../out/synth/synth.ngc
import_files -force -norecurse import_files -force -norecurse
import_files -fileset constrs_1 -force -norecurse /data/joppe/projects/modem/boards/mimas_v1/constraints.ucf import_files -fileset constrs_1 -force -norecurse ../boards/mimas_v1/constraints.ucf
import_as_run -run impl_1 -twx /data/joppe/projects/modem/out/synth/timing.twx /data/joppe/projects/modem/out/synth/synth.ncd import_as_run -run impl_1 -twx ../out/synth/timing.twx ../out/synth/synth.ncd
open_run impl_1