diff --git a/project.cfg b/project.cfg
index 806296a..a587a71 100644
--- a/project.cfg
+++ b/project.cfg
@@ -30,7 +30,7 @@ xst_opts            = -vlgincdir rtl
 files_verilog       = rtl/toplevel/top_generic.v
                       rtl/core/nco_q15.v
 files_con           = boards/mimas_v1/constraints.ucf
-files_other         = 
+files_other         = rtl/util/conv.vh
 
 [target.sim]
 toolchain           = iverilog
@@ -42,4 +42,4 @@ ivl_opts            = -Irtl
 #files_sysverilog    = 
 files_verilog       = sim/tb/tb_nco_q15.v
                       rtl/core/nco_q15.v
-files_other         = 
\ No newline at end of file
+files_other         = rtl/util/conv.vh
\ No newline at end of file
diff --git a/rtl/toplevel/top_generic.v b/rtl/toplevel/top_generic.v
index 1d85f10..85d8d8d 100644
--- a/rtl/toplevel/top_generic.v
+++ b/rtl/toplevel/top_generic.v
@@ -9,7 +9,7 @@ module top_generic(
 
     output wire[5:0] r2r
 );
-
+    `include "util/conv.vh"
     assign led_green = 1'b0;
     assign led_red = 1'b0;
 
@@ -51,16 +51,9 @@ module top_generic(
         .clk_en (clk_en)
     );
 
-    // sin_q15: signed Q15 in [-32768, +32767]
-    wire signed [15:0] s = sin_q15;
-    // Bias to 0..65535 and round before downscaling by 1024 (>>10)
-    wire [16:0] biased = s + 17'sd32768;           // 0..65535
-    wire [5:0] dac_code_next = biased[15:10];     // 0..63 (MSB=bit5)
-    // Register it at the sample rate (clk_en)
     reg [5:0] dac_code;
     always @(posedge aclk) begin
-        if (!aresetn) dac_code <= 6'd0;
-        else dac_code <= dac_code_next;
+        dac_code <= q15_to_uq16(sin_q15) >> 10;
     end
     assign r2r = dac_code;
 endmodule
diff --git a/rtl/util/conv.vh b/rtl/util/conv.vh
new file mode 100644
index 0000000..8a6c268
--- /dev/null
+++ b/rtl/util/conv.vh
@@ -0,0 +1,11 @@
+// =============================================================================
+// Convert Q1.15 to a biased UQ0.16 signal
+// =============================================================================
+function [15:0] q15_to_uq16;
+    input [15:0] q15;
+    reg [16:0] biased;
+begin
+    biased = q15 + 17'sd32768;
+    q15_to_uq16 = biased[15:0];
+end
+endfunction
\ No newline at end of file
diff --git a/scripts/planahead.sh b/scripts/planahead.sh
new file mode 100755
index 0000000..446dda2
--- /dev/null
+++ b/scripts/planahead.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+cd build
+. /opt/packages/xilinx/ISE/14.7/ISE_DS/settings64.sh
+planAhead -mode gui -source ../scripts/planahead.tcl 
\ No newline at end of file
diff --git a/scripts/planahead.tcl b/scripts/planahead.tcl
index af42f9b..b3c1eff 100644
--- a/scripts/planahead.tcl
+++ b/scripts/planahead.tcl
@@ -1,6 +1,7 @@
-create_project project_1 /tmp/project_1 -part xc6slx9tqg144-2
+create_project project_1 tmpplanahead -part xc6slx9tqg144-2 -force
 set_property design_mode GateLvl [current_fileset]
-add_files -norecurse /data/joppe/projects/modem/out/synth/synth.ngc
+add_files -norecurse ../out/synth/synth.ngc
 import_files -force -norecurse
-import_files -fileset constrs_1 -force -norecurse /data/joppe/projects/modem/boards/mimas_v1/constraints.ucf
-import_as_run -run impl_1 -twx /data/joppe/projects/modem/out/synth/timing.twx /data/joppe/projects/modem/out/synth/synth.ncd
\ No newline at end of file
+import_files -fileset constrs_1 -force -norecurse ../boards/mimas_v1/constraints.ucf
+import_as_run -run impl_1 -twx ../out/synth/timing.twx ../out/synth/synth.ncd
+open_run impl_1
\ No newline at end of file