Added planahead script and fixed conversion

rtl/toplevel/top_generic.v

@@ -9,7 +9,7 @@ module top_generic(
 
     output wire[5:0] r2r
 );
-
+    `include "util/conv.vh"
     assign led_green = 1'b0;
     assign led_red = 1'b0;
 
@@ -51,16 +51,9 @@ module top_generic(
         .clk_en (clk_en)
     );
 
-    // sin_q15: signed Q15 in [-32768, +32767]
-    wire signed [15:0] s = sin_q15;
-    // Bias to 0..65535 and round before downscaling by 1024 (>>10)
-    wire [16:0] biased = s + 17'sd32768;           // 0..65535
-    wire [5:0] dac_code_next = biased[15:10];     // 0..63 (MSB=bit5)
-    // Register it at the sample rate (clk_en)
     reg [5:0] dac_code;
     always @(posedge aclk) begin
-        if (!aresetn) dac_code <= 6'd0;
-        else dac_code <= dac_code_next;
+        dac_code <= q15_to_uq16(sin_q15) >> 10;
     end
     assign r2r = dac_code;
 endmodule