Added planahead script and fixed conversion

2025-10-06 16:49:28 +02:00
parent 06ef70e1ee
commit 324bb108e3
5 changed files with 24 additions and 15 deletions
--- a/project.cfg
+++ b/project.cfg
@@ -30,7 +30,7 @@ xst_opts            = -vlgincdir rtl
 files_verilog       = rtl/toplevel/top_generic.v
                      rtl/core/nco_q15.v
 files_con           = boards/mimas_v1/constraints.ucf
-files_other         = 
+files_other         = rtl/util/conv.vh

 [target.sim]
 toolchain           = iverilog
@@ -42,4 +42,4 @@ ivl_opts            = -Irtl
 #files_sysverilog    = 
 files_verilog       = sim/tb/tb_nco_q15.v
                      rtl/core/nco_q15.v
-files_other         = 
+files_other         = rtl/util/conv.vh