Added soclet with gpio banks to top

rtl/wb/wb_gpio.v

@@ -8,6 +8,7 @@ module wb_gpio #(
   input  wire [3:0]  i_wb_sel,
   input  wire        i_wb_we,
   input  wire        i_wb_stb,
+  input  wire [31:0] i_gpio,
 
   output reg  [31:0] o_wb_rdt,
   output reg         o_wb_ack,
@@ -34,7 +35,7 @@ module wb_gpio #(
     if (i_wb_rst) begin
       o_wb_rdt <= 32'h0;
     end else if (i_wb_stb && !i_wb_we) begin
-      o_wb_rdt <= o_gpio;
+      o_wb_rdt <= i_gpio;
     end
   end
 
@@ -51,4 +52,4 @@ module wb_gpio #(
     end
   end
 
-endmodule
+endmodule