joppe/fpga_modem
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Added soclet with gpio banks to top

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This commit is contained in:
Joppe Blondel
2026-02-22 20:00:42 +01:00
parent a97028c2ba
commit 20cfece6e3
14 changed files with 321 additions and 172 deletions
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44
rtl/toplevel/top_generic.v
View File

@@ -22,38 +22,36 @@ module top_generic(
.clk_out_15(clk_15)
);
reg [11:0] count;
localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz
reg [16:0] div_counter = 0; // enough bits for 100k (2^17=131072)
reg [31:0] freq;
always @(posedge clk_15) begin
if (!aresetn) begin
div_counter <= 0;
count <= 0;
end else begin
if (div_counter == DIV_MAX) begin
div_counter <= 0;
if (count == 12'd3999)
count <= 0; // wrap at 4000
else
count <= count + 1'b1; // increment every 1 ms
end else begin
div_counter <= div_counter + 1'b1;
end
end
freq <= count;
end
wire [31:0] GPIO_A;
wire [31:0] GPIO_B;
wire [31:0] GPIO_C;
wire [31:0] GPIO_D;
soclet #(
.memfile("../sw/sweep/sweep.hex")
) mcu (
.i_clk(clk_15),
.i_rst(!aresetn),
.i_GPI_A(GPIO_A),
.i_GPI_B(GPIO_B),
.i_GPI_C(GPIO_C),
.i_GPI_D(GPIO_D),
.o_GPO_A(GPIO_A),
.o_GPO_B(GPIO_B),
.o_GPO_C(GPIO_C),
.o_GPO_D(GPIO_D)
);
wire [15:0] sin_q15;
wire clk_en;
nco_q15 #(
.CLK_HZ(15_000_000),
.FS_HZ(40_000)
.FS_HZ(80_000)
) nco (
.clk (clk_15),
.rst_n (aresetn),
.freq_hz(freq),
.freq_hz(GPIO_A),
.sin_q15(sin_q15),
.cos_q15(),
.clk_en (clk_en)

70
rtl/toplevel/top_serv.v
View File

@@ -1,70 +0,0 @@
`timescale 1ns/1ps
module top_generic(
input wire aclk,
input wire aresetn,
output wire led_green,
output wire led_red,
output wire[5:0] r2r
);
// Clocking
wire clk_100;
wire clk_15;
assign clk_100 = aclk;
clk_gen clocking(
.clk_in(clk_100),
.clk_out_15(clk_15)
);
wire [31:0] wb_adr;
wire [31:0] wb_dat;
wire [31:0] wb_rdt;
wire [3:0] wb_sel;
wire wb_we;
wire wb_stb;
wire wb_ack;
wire [31:0] GPIO;
assign led_green = GPIO[0];
assign led_red = GPIO[1];
assign r2r = GPIO[8:2];
serving #(
.memfile("../sw/blinky/blinky.hex"),
.memsize(8192),
.sim(1'b0),
.RESET_STRATEGY("MINI"),
.WITH_CSR(1)
) serv (
.i_clk(clk_15),
.i_rst(!aresetn),
.i_timer_irq(1'b0),
.i_wb_rdt(wb_rdt),
.i_wb_ack(wb_ack),
.o_wb_adr(wb_adr),
.o_wb_dat(wb_dat),
.o_wb_sel(wb_sel),
.o_wb_we(wb_we),
.o_wb_stb(wb_stb)
);
wb_gpio #(
.address(32'h40000000)
) gpio (
.i_wb_clk(clk_15),
.i_wb_rst(!aresetn),
.i_wb_dat(wb_dat),
.i_wb_adr(wb_adr),
.i_wb_we(wb_we),
.i_wb_stb(wb_stb),
.i_wb_sel(wb_sel),
.o_wb_rdt(wb_rdt),
.o_wb_ack(wb_ack),
.o_gpio(GPIO)
);
endmodule