joppe/fpga_modem
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Added soclet with gpio banks to top

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This commit is contained in:
Joppe Blondel
2026-02-22 20:00:42 +01:00
parent a97028c2ba
commit 20cfece6e3
14 changed files with 321 additions and 172 deletions
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86
project.cfg
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@@ -4,12 +4,6 @@ version = 0.1
out_dir = out
build_dir = build
[server]
hostname = localhost
port = 2020
privkey = /home/joppe/.ssh/id_rsa
pubkey = /home/joppe/.ssh/id_rsa.pub
[target.synth]
toolchain = ISE
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
@@ -30,32 +24,7 @@ files_verilog = rtl/util/conv.vh
rtl/core/decimate_by_r_q15.v
rtl/arch/spartan-6/lvds_comparator.v
rtl/arch/spartan-6/clk_gen.v
files_con = boards/mimas_v1/constraints.ucf
files_other = rtl/util/rc_alpha_q15.vh
[target.ip]
toolchain = ISE_IP
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
files_def = boards/mimas_v1/ip/mem_8kx8b.xco
#boards/mimas_v1/ip/clk_gen.xco
[target.serv]
toolchain = ISE
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
toplevel = top_generic
xst_opts = -vlgincdir rtl
files_con = boards/mimas_v1/constraints.ucf
files_other = sw/blinky/blinky.hex
rtl/util/clog2.vh
files_verilog = rtl/serv/serv_aligner.v
rtl/serv/serv_aligner.v
rtl/serv/serv_alu.v
rtl/serv/serv_bufreg.v
rtl/serv/serv_bufreg2.v
@@ -79,9 +48,22 @@ files_verilog = rtl/serv/serv_aligner.v
rtl/serv/servile.v
rtl/serv/serving_ram.v
rtl/serv/serving.v
rtl/arch/spartan-6/clk_gen.v
rtl/wb/wb_gpio.v
rtl/toplevel/top_serv.v
rtl/wb/wb_gpio_banks.v
rtl/core/soclet.v
files_con = boards/mimas_v1/constraints.ucf
files_other = rtl/util/rc_alpha_q15.vh
rtl/util/clog2.vh
sw/blinky/blinky.hex
[target.ip]
toolchain = ISE_IP
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
files_def = boards/mimas_v1/ip/clk_gen.xco
[target.sim]
toolchain = iverilog
@@ -102,39 +84,3 @@ files_verilog = sim/tb/tb_nco_q15.v
sim/overrides/clk_gen.v
files_other = rtl/util/conv.vh
rtl/util/rc_alpha_q15.vh
[target.servsim]
toolchain = iverilog
runtime = all
toplevel = tb_serving
ivl_opts = -Irtl/util
files_other = sw/blinky/blinky.hex
rtl/util/clog2.vh
files_verilog = rtl/serv/serv_aligner.v
rtl/serv/serv_alu.v
rtl/serv/serv_bufreg.v
rtl/serv/serv_bufreg2.v
rtl/serv/serv_compdec.v
rtl/serv/serv_csr.v
rtl/serv/serv_ctrl.v
rtl/serv/serv_debug.v
rtl/serv/serv_decode.v
rtl/serv/serv_immdec.v
rtl/serv/serv_mem_if.v
rtl/serv/serv_rf_if.v
rtl/serv/serv_rf_ram_if.v
rtl/serv/serv_rf_ram.v
rtl/serv/serv_rf_top.v
rtl/serv/serv_state.v
rtl/serv/serv_synth_wrapper.v
rtl/serv/serv_top.v
rtl/serv/servile_arbiter.v
rtl/serv/servile_mux.v
rtl/serv/servile_rf_mem_if.v
rtl/serv/servile.v
rtl/serv/serving_ram.v
rtl/serv/serving.v
rtl/arch/spartan-6/clk_gen.v
rtl/wb/wb_gpio.v
rtl/toplevel/top_serv.v
sim/tb/tb_serving.v